三维集成电路硅通孔容错技术研究

发布时间：2018-07-14 10:03

【摘要】：三维集成电路是延续摩尔定律的重要手段,TSV是三维集成电路的核心部件。作为一种新兴技术,三维集成电路受到越来越多工业界和学术界人士的重视,和二维集成电路不同,三维集成电路借助硅通孔将多个芯片垂直堆叠,具有功耗低,带宽高,面积小,性能好,支持异构集成等优点,然而其制作工艺尚不成熟,TSV的制作工艺和层与层之间的堆叠会导致TSV发生泄漏和电阻开路故障,从而严重影响三维集成电路的良率和可靠性。TSV良率问题成为三维集成电路商品化的主要制约因素。本文的主要研究内容如下：1)认真学习三维集成电路的基础知识和分析三维集成电路的优点,重点探索影响三维集成电路良率的TSV缺陷。分析TSV缺陷所引起的TSV故障,用HSPICE对TSV的故障进行参数建模,并分析故障TSV的故障效应。2)学习现有的TSV容错方法,按照其对TSV的容错机理,按容错机理将其分为测试容错和在线容错两种类型,着重研究这两种容错方案的优缺点。基于现有理论研究新的TSV在线容错方案。3)针对三维集成电路中硅通孔(TSV)良率不高的问题和以前方法存在的不足,提出一种双TSV在线自容错方案。该方案采用相互耦合的通道结构,能减小TSV的失效概率；通过设计容错结构来实现对TSV泄漏和电阻开路故障的自动修复。理论分析和实验结果表明：该方案可在无测试时间和电路端口开销且不中断电路正常工作的前提下,对TSV的泄漏和电阻开路两种故障进行在线容错,有效提高三维集成电路的良率和可靠性。
[Abstract]:Three-dimensional integrated circuit is an important means to extend Moore's law. TSV is the core component of three-dimensional integrated circuit. As a new technology, 3D integrated circuit has attracted more and more attention from industry and academic circles. Unlike two-dimensional integrated circuit, 3D integrated circuit uses silicon through hole to stack several chips vertically, which has low power consumption and high bandwidth. The advantages of small area, good performance and support for heterogeneous integration, however, the fabrication process of TSV and stacking between layers will lead to leakage and resistance open circuit failure of TSV. Therefore, the problem of the yield and reliability of 3D integrated circuits. TSV yield has become the main restricting factor for the commercialization of 3D integrated circuits. The main contents of this paper are as follows: (1) to study the basic knowledge of 3D integrated circuits and analyze the advantages of 3D integrated circuits, especially to explore the TSV defects that affect the yield of 3D integrated circuits. The TSV fault caused by TSV defect is analyzed, the parameter model of TSV fault is modeled by HSPICE, and the fault effect of TSV fault is analyzed. 2) the existing TSV fault tolerant method is studied, according to its fault tolerance mechanism for TSV, According to the fault-tolerant mechanism, it is divided into two types: test fault-tolerant and on-line fault-tolerant, and the merits and demerits of these two fault-tolerant schemes are studied emphatically. Based on the existing theoretical study of a new TSV fault tolerance scheme (TSV), a dual TSV online fault tolerance scheme is proposed to solve the problem of low yield of silicon through hole (TSV) in 3D integrated circuits and the shortcomings of previous methods. In this scheme, the mutual coupling channel structure is used to reduce the failure probability of TSV, and the fault tolerant structure is designed to automatically repair the TSV leakage and resistance open circuit faults. The theoretical analysis and experimental results show that the proposed scheme can be used for on-line fault tolerance of TSV leakage and resistance open circuit without testing time, circuit port overhead and circuit normal operation. Improve the yield and reliability of three-dimensional integrated circuit effectively.
【学位授予单位】：合肥工业大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TN40

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