基于JESD204B协议的频率综合器的设计

发布时间：2018-07-16 16:43

【摘要】：频率综合器通过结合倍频、分频和混频几种操作来得到所需的信号,现在广泛的应用在各种通信设备和电子产品中。而电荷泵锁相环型(CPPLL,Charge Pump Phase-Locked-Loop)的频率综合器是其中结构简单,性能高的频率综合电路,它产生的频率信号稳定且精确,能为系统提供稳定可靠的信号源。同时,锁相环型频率综合器能同时产生多个不同频率值的信号,而且本文锁相环采用的是环型VCO(Voltage Controlled Oscillator),占用面积小,易于片上集成。如今,随着通信技术的飞速发展,通信系统要求低的相位噪声、窄的信道步长、高的输出频率和更快的响应时间等等,因此,作为系统中重要的信号源产生模块,设计高性能的锁相环型频率综合器也将面临越来越多的挑战。本文研究设计的CPPLL频率综合器是基于JESD204B协议的,根据系统要求,需要产生4相、1 GHz的差分时钟信号,和100 MHz的系统时钟信号。设计采用SMIC 0.13μm CMOS 1P8M工艺,整个芯片工作在1.2 V电压下,最终芯片面积为0.12 2mm,电流为22 mA,能在5?s内锁定并且能稳定输出系统要求的时钟信号,测试出来的周期时钟抖动为78.15ps。
[Abstract]:Frequency synthesizer is widely used in various communication equipments and electronic products to get the needed signal by combining the operation of frequency doubling, frequency division and mixing. The frequency synthesizer of CPPLL charge Pump Phase-Locked-Loop is a frequency synthesizer with simple structure and high performance. Its frequency signal is stable and accurate, and it can provide a stable and reliable signal source for the system. At the same time, the PLL frequency synthesizer can produce multiple signals with different frequency values at the same time. The PLL in this paper uses the loop VCO (Voltage Controlled Oscillator), which occupies a small area and is easy to be integrated on a chip. Nowadays, with the rapid development of communication technology, the communication system requires low phase noise, narrow channel step size, high output frequency and faster response time, etc. Therefore, as an important signal source generation module in the system, The design of high performance PLL frequency synthesizer will face more and more challenges. The CPPLL frequency synthesizer designed in this paper is based on JESD204B protocol. According to the requirement of the system, the differential clock signal of 4 phase and 1 GHz and 100 MHz system clock signal should be generated. The design adopts SMIC 0.13 渭 m CMOS 1P8M technology. The whole chip works at 1.2 V voltage, the final chip area is 0.122 mm, the current is 22 Ma. The chip can be locked in 5s and can output the required clock signal stably. The measured periodic clock jitter is 78.15ps.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN74

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