协同缓解电路NBTI效应与泄漏功耗技术研究
发布时间：2018-07-21 22:08
【摘要】：随着集成电路的工艺水平进入到纳米层级时,器件的诸多负面效应逐渐突显出来,其中负偏置温度不稳定性(Negative Bias Temperature Instability, NBTI)效应成为影响集成电路可靠性与使用寿命的重要因素之一。长期的NBTI效应会造成电路的时延增加,速度降低,并最终导致电路的功能失效。针对NBTI效应的分析与研究已成为集成电路抗老化设计的重要课题之一。同时,电压的非等比缩小带来较大的泄漏功耗(Leakage Power),严重影响到器件的使用寿命,研究如何降低电路的泄漏功耗也是低功耗设计领域的重要内容之一。现有方案通过输入向量控制(IVC)结合门替换(GR)技术缓解负偏置温度不稳定性(NBTI)引起的电路老化,却存在GR应用可能破坏IVC抗老化效果的问题,本文提出了一种输入向量控制与传输门(TG)插入相结合的方案来缓解电路的NBTI效应,对于切分的子电路动态回溯寻找其最优输入向量,在不破坏IVC优化效果的情况下,通过插入传输门来消除合并子电路时产生的逻辑冲突,最终得到复原后的目标电路的最优输入控制向量。实验结果表明:本文的IVC与传输门结合方案对于电路的时延退化改善率为57.74%,面积开销为1.69%,与IVC与GR方案相比,时延退化改善率提高0.67倍,面积开销降低0.42倍,体现了本文方案能够更好的缓解电路的NBTI老化效应。本文的IVC与传输门插入方案仅考虑到对于NBTI效应的缓解,却未能减少电路的静态泄漏功耗,为了满足集成电路设计的低功耗要求,本文给出了协同缓解电路NBTI与降低泄漏功耗方案,在IVC与传输门插入方案基础上加以操作;当寻找子电路最优输入向量时,在非关键路径上降低电路的泄漏功耗,同时在关键路径上,基于缓解电路NBTI效应的基础上进一步减少泄漏功耗,最终通过合并子电路得到最优输入向量来协同缓解电路的NBTI效应与降低泄漏功耗。相比较IVC与GR的协同优化方案,本文方案在电路泄漏功耗几乎相同的前提下,时延退化改善率提高了 0.51倍,更加有利于NBTI效应的缓解与泄漏功耗的降低。
[Abstract]:As the process level of integrated circuits reaches the nanometer level, many negative effects of the devices gradually become apparent. The negative bias temperature instability (NBTI) effect is one of the most important factors affecting the reliability and service life of integrated circuits. The long term NBTI effect will lead to the increase of delay and the decrease of the speed of the circuit, and ultimately lead to the functional failure of the circuit. The analysis and research of NBTI effect has become one of the most important topics in the design of integrated circuits. At the same time, the reduction of voltage non-equal ratio brings a large leakage power (Leakage Power), which seriously affects the service life of the device. The research on how to reduce the leakage power is also one of the important contents in the field of low-power design. The current scheme uses input vector control (IVC) combined with gate substitution (gr) to mitigate the circuit aging caused by negative bias temperature instability (NBTI), but there is a problem that the application of gr may undermine the anti-aging effect of IVC. In this paper, a scheme combining input vector control and transmission gate (TG) insertion is proposed to mitigate the NBTI effect of the circuit. The optimal input control vector of the restored target circuit is obtained by inserting the transmission gate to eliminate the logic conflict caused by the merging sub-circuit. The experimental results show that the time delay degradation improvement rate of the proposed IVC and transmission gate scheme is 57.74 and the area overhead is 1.69. Compared with the IVC and gr scheme, the delay degradation improvement rate is 0.67 times higher and the area cost is reduced by 0.42 times. This scheme can better alleviate the NBTI aging effect of the circuit. The IVC and transmission gate insertion scheme in this paper only considers the mitigation of NBTI effect, but fails to reduce the static leakage power consumption of the circuit. In order to meet the low power requirement of integrated circuit design, the IVC and the transmission gate insert scheme only consider the mitigation of NBTI effect. In this paper, the cooperative mitigation circuit NBTI and the scheme of reducing leakage power consumption are presented, which are operated on the basis of IVC and transmission gate insertion scheme, and when the optimal input vector of sub-circuit is found, the leakage power consumption of the circuit is reduced on the non-critical path. At the same time, based on the NBTI effect of the mitigation circuit, the leakage power is further reduced on the critical path. Finally, the optimal input vector is obtained by combining the subcircuits to coordinate the NBTI effect and the leakage power loss of the mitigation circuit. Compared with IVC and gr cooperative optimization schemes, the proposed scheme can improve the rate of delay degradation by 0.51 times on the premise of almost the same leakage power consumption, which is more conducive to the mitigation of NBTI effect and the reduction of leakage power consumption.
【学位授予单位】：合肥工业大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN402
本文编号：2137011
[Abstract]:As the process level of integrated circuits reaches the nanometer level, many negative effects of the devices gradually become apparent. The negative bias temperature instability (NBTI) effect is one of the most important factors affecting the reliability and service life of integrated circuits. The long term NBTI effect will lead to the increase of delay and the decrease of the speed of the circuit, and ultimately lead to the functional failure of the circuit. The analysis and research of NBTI effect has become one of the most important topics in the design of integrated circuits. At the same time, the reduction of voltage non-equal ratio brings a large leakage power (Leakage Power), which seriously affects the service life of the device. The research on how to reduce the leakage power is also one of the important contents in the field of low-power design. The current scheme uses input vector control (IVC) combined with gate substitution (gr) to mitigate the circuit aging caused by negative bias temperature instability (NBTI), but there is a problem that the application of gr may undermine the anti-aging effect of IVC. In this paper, a scheme combining input vector control and transmission gate (TG) insertion is proposed to mitigate the NBTI effect of the circuit. The optimal input control vector of the restored target circuit is obtained by inserting the transmission gate to eliminate the logic conflict caused by the merging sub-circuit. The experimental results show that the time delay degradation improvement rate of the proposed IVC and transmission gate scheme is 57.74 and the area overhead is 1.69. Compared with the IVC and gr scheme, the delay degradation improvement rate is 0.67 times higher and the area cost is reduced by 0.42 times. This scheme can better alleviate the NBTI aging effect of the circuit. The IVC and transmission gate insertion scheme in this paper only considers the mitigation of NBTI effect, but fails to reduce the static leakage power consumption of the circuit. In order to meet the low power requirement of integrated circuit design, the IVC and the transmission gate insert scheme only consider the mitigation of NBTI effect. In this paper, the cooperative mitigation circuit NBTI and the scheme of reducing leakage power consumption are presented, which are operated on the basis of IVC and transmission gate insertion scheme, and when the optimal input vector of sub-circuit is found, the leakage power consumption of the circuit is reduced on the non-critical path. At the same time, based on the NBTI effect of the mitigation circuit, the leakage power is further reduced on the critical path. Finally, the optimal input vector is obtained by combining the subcircuits to coordinate the NBTI effect and the leakage power loss of the mitigation circuit. Compared with IVC and gr cooperative optimization schemes, the proposed scheme can improve the rate of delay degradation by 0.51 times on the premise of almost the same leakage power consumption, which is more conducive to the mitigation of NBTI effect and the reduction of leakage power consumption.
【学位授予单位】：合肥工业大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN402
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