基于时钟偏斜调度的VLSI时序优化方法研究

发布时间：2018-07-22 19:12

【摘要】：在数字集成电路设计中,时钟信号的特性和分布网络对芯片设计至关重要。当前的时钟树综合,都以零时钟偏斜(Zero Clock Skew)为优化目标,但这种零偏斜的时钟树结构并不一定最优。本文以非零时钟偏斜为研究背景,重点分析时钟偏斜对电路时序和稳定性的影响,论文主要研究内容可分为以下几个部分:(1)首先介绍时钟偏斜产生的原因以及传统时钟树综合策略对时钟偏斜的处理方法。对触发器电路和锁存器电路的工作原理和时序特性深入分析,总结出时钟偏斜与时钟周期之间的约束关系。(2)研究传统零时钟偏斜下的时序优化方法:流水线(Pipelining)和重定时(Retiming)技术,分析了这两种时序优化方法的应用范围以及存在的不足,进而研究时钟偏斜调度(Clock Skew Scheduling)对电路时序所产生的影响。(3)根据时钟偏斜对电路时序的优化原理,借助IBM CPLEX优化软件,实现了最小时钟周期的时钟偏斜调度方法,完成了对触发器电路和锁存器电路的时序优化。选取ISCAS’89基准电路对优化方法进行测试,实验结果表明,相比传统的零时钟偏斜方法,时钟偏斜调度所优化的触发器电路能够提升约28%的时序性能,对锁存器电路能够提升约14%的时序性能。(4)研究了时钟偏斜调度对电路稳定性的影响,实现了时钟偏斜调度的安全域补偿法与成本函数法,并对电路进行测试。实验结果表明,两种方法对稳定性的改善都以牺牲时序性能作为代价,无法同时优化时序和稳定性。(5)延时插入方法(Delay Insertion)常用于修复时序违规,改善电路稳定性,论文提出了时钟偏斜调度的延时插入方法,研究和分析了该方法对电路时序和稳定性的影响,并实现了对时序和稳定性的同时优化。对ISCAS’89电路的实验结果表明,触发器和锁存器电路能够在最小时钟周期下提升约10%的稳定性。
[Abstract]:In the design of digital integrated circuit, the characteristic of clock signal and distribution network are very important to chip design. In the current clock tree synthesis, the zero clock skew (ZCS) is used as the optimization target, but the zero-skew clock tree structure is not always optimal. In this paper, the influence of clock skew on the timing and stability of the circuit is analyzed based on the non-zero clock skew. The main contents of this paper can be divided into the following parts: (1) the causes of clock skew and the processing method of clock skew by traditional clock tree synthesis strategy are introduced. The working principle and timing characteristics of flip-flop circuit and latch circuit are deeply analyzed, and the constraint relationship between clock skew and clock period is summarized. (2) the traditional timing optimization methods under zero clock skew are studied: pipelining and retiming techniques. This paper analyzes the scope of application and the shortcomings of these two methods, and then studies the influence of clock skew scheduling on circuit timing. (3) according to the optimization principle of clock skew, the optimization software IBM CPLEX is used to optimize the circuit timing. The clock skew scheduling method with minimum clock cycle is implemented, and the timing optimization of trigger circuit and latch circuit is completed. The ISCAS-89 reference circuit is selected to test the optimization method. The experimental results show that compared with the traditional zero-clock skew method, the trigger circuit optimized by clock skew scheduling can improve the timing performance by about 28%. The timing performance of latch circuits can be improved by about 14%. (4) the effects of clock skew scheduling on the stability of the circuits are studied. The security domain compensation method and cost function method of clock skew scheduling are realized and the circuits are tested. Experimental results show that both methods can not optimize timing and stability at the expense of timing performance. (5) delay insertion is often used to repair timing violations and improve circuit stability. In this paper, a time-delay insertion method for clock skew scheduling is proposed, and the influence of this method on the timing and stability of the circuit is studied and analyzed, and the timing and stability optimization is realized. The experimental results of the ISCAS-89 circuit show that the flip-flop and latch circuit can improve the stability by about 10% under the minimum clock period.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN47

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