1700V 4H-SiC DMOS晶体管的设计和实验研究
发布时间：2018-07-30 07:53
【摘要】：碳化硅(Silicon Carbide)半导体材料凭借临界击穿电场高、热导率高、热载流子饱和漂移速度高、抗辐照能力强等特点,已经成为国际功率半导体领域的研究热点。与Si基功率器件相比,Si C功率半导体器件及模块不仅功率更大,而且开关损耗和系统体积也降低一半以上。国内在SiC MOSFET功率器件的研究方面才刚刚起步,与国际水平差距还比较显著。本文立足于国内科研单位的工艺平台,设计优化了击穿电压1700V 4H-SiC DMOS晶体管结构参数,绘制了器件版图,并进行了流片实验验证和测试分析,为后续国内1700V SiC DMOS晶体管的应用研究提供了理论支持和技术指导。本论文首先利用半导体二维数值分析软件Silvaco的器件模拟模块Atlas对击穿电压1700V的4H-SiC DMOS元胞结构参数进行设计,折衷优化栅氧化层厚度、JFET宽度、沟道长度和P_base区浓度等器件结构参数对击穿电压、阈值电压和导通电阻的影响。其次在确定元胞参数后,考虑到曲率效应,分别研究了场板终端、单步刻蚀型JTE终端和场限环终端对器件击穿电压的影响。此外,针对高电场应力下Si C DMOS器件的栅介质容易发生FN隧穿,从而降低器件可靠性的问题,研究了一种降低FN隧穿效应的基于SiO2和HfO2等高K材料组成的SiC MOS复合栅结构。接下来本文对经过1300℃高温氧化并在NO气体中退火的4H-SiC MOS电容界面特性进行研究。测试结果表明,高温氧化后NO退火能够降低SiO2/SiC界面态密度,而且随着退火温度和时间的提高,界面态密度会进一步降低。最后基于器件仿真设计,绘制出1700V 4H-SiC DMOS器件版图,同时立足于国内科研院所的工艺平台,进行了流片实验和测试结果分析。实验流片出来的4H-Si C DMOS器件击穿电压达到2500V,阈值电压4.8V,达到设计目标,为后续开展1700V的SiC DMOS器件产业化的研究提供了有力支撑。
[Abstract]:Silicon carbide (sic) (Silicon Carbide) semiconductor material has become a research hotspot in the field of power semiconductor because of its high critical breakdown electric field, high thermal conductivity, high saturation drift velocity of hot carriers, strong radiation resistance and so on. Compared with Si-based power devices, Si C power semiconductor devices and modules not only have higher power, but also reduce switching loss and system volume by more than half. The research of SiC MOSFET power devices in China has just started, and the gap with the international level is significant. Based on the technology platform of domestic scientific research units, this paper designs and optimizes the structure parameters of 1700V 4H-SiC DMOS transistor, draws the layout of the device, and carries out the verification and test analysis of the flow sheet experiment. It provides theoretical support and technical guidance for the application research of 1700V SiC DMOS transistors in China. In this paper, the device simulation module Atlas of semiconductor two-dimensional numerical analysis software Silvaco is used to design the cell structure parameters of 4H-SiC DMOS with a breakdown voltage of 1700V, and the thickness of gate oxide is optimized to optimize the width of JFET. The influence of channel length and P_base concentration on breakdown voltage, threshold voltage and on-resistance. Secondly, after determining the cell parameters and considering the curvature effect, the effects of field board terminal, single-step etching JTE terminal and field limiting loop terminal on the breakdown voltage of the device are studied respectively. In addition to the problem that FN tunneling is easy to occur in the gate dielectric of Si C DMOS devices under high electric field stress thus reducing the reliability of FN devices a SiC MOS composite gate structure based on high K materials such as SiO2 and HfO2 is studied to reduce the FN tunneling effect. The interface characteristics of 4H-SiC MOS capacitors after high temperature oxidation at 1300 鈩，
本文编号：2154337
[Abstract]:Silicon carbide (sic) (Silicon Carbide) semiconductor material has become a research hotspot in the field of power semiconductor because of its high critical breakdown electric field, high thermal conductivity, high saturation drift velocity of hot carriers, strong radiation resistance and so on. Compared with Si-based power devices, Si C power semiconductor devices and modules not only have higher power, but also reduce switching loss and system volume by more than half. The research of SiC MOSFET power devices in China has just started, and the gap with the international level is significant. Based on the technology platform of domestic scientific research units, this paper designs and optimizes the structure parameters of 1700V 4H-SiC DMOS transistor, draws the layout of the device, and carries out the verification and test analysis of the flow sheet experiment. It provides theoretical support and technical guidance for the application research of 1700V SiC DMOS transistors in China. In this paper, the device simulation module Atlas of semiconductor two-dimensional numerical analysis software Silvaco is used to design the cell structure parameters of 4H-SiC DMOS with a breakdown voltage of 1700V, and the thickness of gate oxide is optimized to optimize the width of JFET. The influence of channel length and P_base concentration on breakdown voltage, threshold voltage and on-resistance. Secondly, after determining the cell parameters and considering the curvature effect, the effects of field board terminal, single-step etching JTE terminal and field limiting loop terminal on the breakdown voltage of the device are studied respectively. In addition to the problem that FN tunneling is easy to occur in the gate dielectric of Si C DMOS devices under high electric field stress thus reducing the reliability of FN devices a SiC MOS composite gate structure based on high K materials such as SiO2 and HfO2 is studied to reduce the FN tunneling effect. The interface characteristics of 4H-SiC MOS capacitors after high temperature oxidation at 1300 鈩，
本文编号：2154337
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