超高速TIADC采样系统通道失配校正技术研究

发布时间：2018-08-01 16:32

【摘要】：高速采样广泛应用于通信、雷达等领域,然而受到工艺的制约,单片模数转换(Analog to Digital Converter,简称ADC)芯片无法同时满足高采样率和高分辨率的需求。时间交替采样技术技术(Time-Interleaved ADC Ssytems,简称TIADC)通过使用多片同种ADC芯片同时对一个信号进行交错采样,在分辨率不降低的情况下使系统的采样率成倍提高,然而多片ADC芯片的不一致性会导致多个通道间的失配。这些失配主要包括芯片初始偏置电压不同引起的偏置失配、芯片增益量不同引起的增益失配、各芯片采样时钟相位差异引起的时间失配。三种通道失配会使各通道采样数据重组时无法正确匹配,从而导致系统不能正确还原原始波形,降低系统的性能。针对8通道8GSPS采样率的TIADC系统,本论文主要进行了如下的工作来校正三种失配,保证系统的性能。1)研究分析了三种失配与通道数、采样率之间的关系,结合本论文所研究的系统的特点,在数学上推导了三种失配对本系统的影响,并提出了相应的校正方案。2)分析了各种通道失配误差的获取方法,结合本论文所研究系统的特点对这些方法进行了比较,选择了最合适的正弦拟合法。之后分析了正弦拟合法的优缺点,并结合实际提出了引入信号频率作为估计量的四参数正弦拟合法。3)根据三种误差的自身特性,并结合本论文所研究系统的通道数、采样率,设计了前端数据时钟自同步法来同步各通道采样数据,消除通道间采样时钟偏斜；提出了结合加法器、乘法器和FARROW结构全通滤波器的综合校正方法,实现了对采样数据的后端数字校正。并设计了一系列的试验进行了验证。
[Abstract]:High-speed sampling is widely used in communication, radar and other fields. However, due to the limitation of technology, the single-chip analog-to-digital conversion (Analog to Digital Converter, (ADC) chip can not meet the needs of high sampling rate and high resolution at the same time. Time-Interleaved ADC Ssytems (TIADC) by using the same kind of ADC chip to interlaced the same signal at the same time, the sampling rate of the system can be increased exponentially under the condition that the resolution is not reduced. However, the inconsistency of multiple ADC chips can lead to mismatch between multiple channels. These mismatches mainly include the bias mismatch caused by the different initial bias voltage, the gain mismatch caused by the chip gain, and the time mismatch caused by the different sampling clock phase of each chip. The mismatch of the three channels can make the data of each channel not match correctly, which leads to the system can not restore the original waveform correctly and reduce the performance of the system. For the TIADC system with 8-channel 8GSPS sampling rate, the main work of this paper is to correct the three mismatches and ensure the performance of the system. (1) the relationship between the three mismatches and the number of channels and the sampling rate is studied and analyzed. According to the characteristics of the system studied in this paper, the influence of three mismatches on the system is derived mathematically, and the corresponding correction scheme .2) is analyzed to obtain various channel mismatch errors. These methods are compared according to the characteristics of the system studied in this paper, and the most suitable sinusoidal fitting method is selected. Then, the advantages and disadvantages of sinusoidal fitting method are analyzed, and a four-parameter sinusoidal fitting method with signal frequency as the estimator is proposed according to the characteristics of the three kinds of errors, and the number of channels and the sampling rate of the system studied in this paper. The front end data clock self-synchronization method is designed to synchronize the sampling data of each channel to eliminate the sampling clock skew between channels, and a comprehensive correction method combining adder, multiplier and FARROW structure all-pass filter is proposed. The back end digital correction of the sampled data is realized. A series of experiments were designed to verify the results.
【学位授予单位】：浙江大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TN792

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