多核混合可重构计算系统的设计与优化

发布时间：2018-08-06 19:39

【摘要】：随着半导体行业的发展和电子设计自动化技术进步,芯片容量按照摩尔定律每18个月增长一倍,而应用的计算量却以几何指数增加。限于器件工艺技术,单纯通过提高单核芯片主频,已经无法满足现代应用计算复杂、数据量大、实时性要求高的特点。在此背景下,多种新型的系统架构应运而生,新型计算技术的发展也日趋成熟。本文设计并优化了基于FPGA的多核混合可重构计算系统,可稳定地运行在100MHz时钟频率下。在优化前后的系统上完成多种浮点密集型计算应用,既验证了系统计算的正确性,又证明了优化策略的可行性。论文的主要工作如下：1.总结了可重构计算以及多核技术的发展和研究现状,根据多核可重构计算系统的设计方向设计了可重构计算系统模型。2.设计并优化可重构计算核,主要包括可重构计算阵列和流水线。流水线主要用于执行不合适可重构计算处理的离散和控制指令,增加了系统对算法的适应性,提高了系统的计算效率。同时针对两者的特点提出了多种优化策略。3.设计了片上网络作为多个计算核心进行并行计算所需的高效通信架构,支持多路数据并行传输；通过优化硬件控制逻辑和采用合理的存储空间设计有效减少了数据通信时间,提升了计算效率。4.通过在优化前后的系统上映射浮点矩阵乘法、矩阵求逆、实对称矩阵特征分解以及运动评估算法,验证了原型系统的高效性和灵活性,以及优化策略的良好效果。
[Abstract]:With the development of semiconductor industry and the advance of electronic design automation technology, the chip capacity has doubled every 18 months according to Moore's law, while the computational complexity of application has increased by geometric exponent. Limited to the device technology, it can not meet the requirements of modern application such as complex calculation, large amount of data and high real-time performance simply by improving the main frequency of single core chip. Under this background, many kinds of new system architecture emerge as the times require, and the development of new computing technology is maturing day by day. This paper designs and optimizes a multi-core hybrid reconfigurable computing system based on FPGA, which can run stably at 100MHz clock frequency. A variety of floating-point intensive computing applications are completed in the system before and after optimization, which not only verifies the correctness of the system calculation, but also proves the feasibility of the optimization strategy. The main work of the thesis is as follows: 1: 1. This paper summarizes the development and research status of reconfigurable computing and multi-kernel technology, and designs a reconfigurable computing system model .2. according to the design direction of multi-core reconfigurable computing system. Reconfigurable computing cores are designed and optimized, including reconfigurable computing arrays and pipelining. Pipelining is mainly used to execute discrete and control instructions which are not suitable for reconfigurable computation processing. It increases the adaptability of the system to the algorithm and improves the efficiency of the system. At the same time, according to the characteristics of the two, we put forward a variety of optimization strategies. An efficient communication architecture for parallel computing is designed, which supports multi-channel parallel data transmission, and reduces the time of data communication by optimizing hardware control logic and adopting reasonable storage space design. Improved computational efficiency. 4. By mapping floating-point matrix multiplication, matrix inversion, real symmetric matrix characteristic decomposition and motion evaluation algorithm on the system before and after optimization, the efficiency and flexibility of the prototype system and the good effect of the optimization strategy are verified.
【学位授予单位】：合肥工业大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN791

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