UVM验证方法学在SSD主控SoC芯片验证中的应用
发布时间：2018-08-10 20:55
【摘要】：目前,随着SoC (System on Chip)芯片规模及复杂度的快速增长,传统的验证技术已经不能满足项目进度的需求。而且由于IP复用技术的广泛应用,工程师往往不得不花费大量的时间去了解IP核设计细节,并为其开发复杂的验证平台和测试激励。面对巨大的验证压力,验证业界开发出了一套新的验证方法学UVM (Universal Verification Methodology),它有着强大的、已证实的工业基础,是未来验证技术的发展趋势。本文在详细介绍UVM验证方法学的核心思想和寄存器模型的基础上,采用UVM验证方法搭建了SSD(Solid State Disk)主控SoC芯片的验证平台,包括可重用接口UVCs (UVM Verification Component)、模块和系统UVCs以及系统寄存器模型等。通过分析芯片的系统架构和功能需求,提炼出芯片待验证功能点,并利用搭建好的验证平台对芯片进行验证,给出了各模块的验证结果以及覆盖率分析。本课题所设计的UVM验证平台具有高效率、高可重用性的特点,其支持受约束激励自动生成、自动检测和功能覆盖率等功能,大大提高了验证的完备性和效率。并且验证平台可随时按需求定制平台架构、添加相关验证组件UVC、修改随机向量约束条件等,使其可重用性和灵活性最大化。另外,寄存器模型为验证平台提供了一个方便跟踪和访问DUT内部寄存器的方法,可用于监控待验证芯片行为和生成更高抽象层次的激励。本文所研究的验证方法高效且实用,可应用于其它SSD主控芯片或类似芯片的验证当中。
[Abstract]:At present, with the rapid growth of SoC (System on Chip) chip size and complexity, the traditional verification technology can not meet the needs of project schedule. Because of the wide application of IP reuse technology, engineers often have to spend a lot of time to understand the details of IP core design, and develop complex verification platform and test incentives for it. In the face of great verification pressure, the verification industry has developed a new verification methodology, UVM (Universal Verification Methodology), which has a strong and proven industrial foundation, and is the development trend of verification technology in the future. On the basis of introducing the core idea and register model of UVM verification methodology in detail, this paper uses UVM verification method to build the verification platform of SSD (Solid State Disk) master SoC chip. It includes reusable interface UVCs (UVM Verification Component), module and system UVCs, system register model and so on. By analyzing the system architecture and functional requirements of the chip, the functional points of the chip to be verified are extracted, and the verification results and coverage analysis of each module are given by using a good verification platform. The UVM verification platform designed in this paper has the characteristics of high efficiency and high reusability. It supports the functions of automatic generation of constrained excitation, automatic detection and function coverage, which greatly improves the completeness and efficiency of verification. And the verification platform can customize the platform architecture according to the demand at any time, add the related verification component UVC, modify the constraint condition of random vector, etc., make its reusability and flexibility maximized. In addition, the register model provides a convenient way to track and access the internal register of DUT for the verification platform, which can be used to monitor the behavior of the chip to be verified and to generate a higher abstract level of excitation. The verification method studied in this paper is efficient and practical, and can be applied to other SSD master chips or similar chips.
【学位授予单位】：东南大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN47
本文编号：2176180
[Abstract]:At present, with the rapid growth of SoC (System on Chip) chip size and complexity, the traditional verification technology can not meet the needs of project schedule. Because of the wide application of IP reuse technology, engineers often have to spend a lot of time to understand the details of IP core design, and develop complex verification platform and test incentives for it. In the face of great verification pressure, the verification industry has developed a new verification methodology, UVM (Universal Verification Methodology), which has a strong and proven industrial foundation, and is the development trend of verification technology in the future. On the basis of introducing the core idea and register model of UVM verification methodology in detail, this paper uses UVM verification method to build the verification platform of SSD (Solid State Disk) master SoC chip. It includes reusable interface UVCs (UVM Verification Component), module and system UVCs, system register model and so on. By analyzing the system architecture and functional requirements of the chip, the functional points of the chip to be verified are extracted, and the verification results and coverage analysis of each module are given by using a good verification platform. The UVM verification platform designed in this paper has the characteristics of high efficiency and high reusability. It supports the functions of automatic generation of constrained excitation, automatic detection and function coverage, which greatly improves the completeness and efficiency of verification. And the verification platform can customize the platform architecture according to the demand at any time, add the related verification component UVC, modify the constraint condition of random vector, etc., make its reusability and flexibility maximized. In addition, the register model provides a convenient way to track and access the internal register of DUT for the verification platform, which can be used to monitor the behavior of the chip to be verified and to generate a higher abstract level of excitation. The verification method studied in this paper is efficient and practical, and can be applied to other SSD master chips or similar chips.
【学位授予单位】：东南大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN47
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