基质辅助激光解析仪高速数据采集系统设计和实现
发布时间：2018-08-10 21:02
【摘要】：生物安全是指生物性的传染媒介通过直接感染或间接破坏环境而导致对人类、动物或植物的直接或潜在的威胁。通过研究发现,传染媒介大部分是由微生物引起的。由于微生物种类繁多,且容易发生突变,在面对突发生物安全事件时,需要迅速确定微生物的种类及来源,才能够采取有效措施抑制传染媒介的扩散和发展,因此安全、可靠、快速、准确的微生物检测技术是生物安全领域中亟待解决的关键问题之一。传统微生物检测技术具有易污染、周期长、灵敏度低等特点,而国外使用的基于微生物表达谱的生物质谱分析技术可实现对微生物的现场快速、准确的鉴定、分类、溯源和监测,具有传统微生物检测技术不可比拟的优势,为生物安全等领域提供了一种强有力的分析测试手段,但对我国采取了核心技术封锁策略,因此开发具有核心自主知识产权的创新微生物检测设备和配套技术体系已成为我国生物安全领域研究的重要课题。本论文所研究的高速数据采集系统是国家重大科学仪器设备开发专项“生物安全专用基质辅助激光解析仪的开发及应用(2012YQ180117)”中的重要组成部分之一。基质辅助激光解析电离化/飞行时间质谱(MALDI-TOF-MS)是近年来快速发展起来的一种新型软电离生物质谱,具有灵敏度高、准确度高及分辨率高等特点。MALDI-TOF-MS由进样系统、基质辅助激光解析离子源、飞行时间质量分析器和离子束流高速采集等几部分组成。离子束流高速采集包括离子检测器和高速数据采集系统两部分,其中高速数据采集系统完成对检测器输出的离子脉冲信号的数据采集、传输、处理、分析等。准确测量离子脉冲信号是获得高质量质谱数据的关键环节。高频微弱离子脉冲信号的测量包括微弱信号调理电路、高速ADC数据采集、数据存储、数据上传处理分析等。为提高离子脉冲信号测量精度,本文以FPGA作为主控芯片,利用过采样技术提高信噪比,即将ADC采样率设定为2Gsps,同时设定ADC分辨率为12bit,并配合数据采集传输扩展相应存储容量和高速传输接口,实现对离子脉冲信号的快速、高精度测量。本论文的具体研究内容包括:1.高速数据采集系统方案设计。从满足MALDI-TOF-MS中离子脉冲信号检测要求出发,首先确定了高速数据采集系统硬件电路构成形式。该硬件电路主要包括FPGA主控电路、信号调理电路、ADC采样电路、DDR2 SDRAM存储电路、千兆以太网电路、ADC时钟电路,及所需电源电路等。其中FPGA主控电路实现对整个高速数据采集系统的逻辑控制;信号调理电路主要对MALDI-TOF-MS检测器输出的最大幅值为10mA的离子脉冲信号进行电流转电压、微弱信号放大、同时为与ADC输入方式配合将信号由单端输出转为差分输出;高速ADC模块对调理输出信号进行高速采样,将离子脉冲信号转换成数字信号;DDR2 SDRAM存储电路实现对采样数据的缓存,同时降低数据的实时传输速率。为提高被测样品离子脉冲信号测量信噪比,需对同一样品的多次离子脉冲信号采样后进行数据叠加处理,在FPGA内部存储空间无法满足情况下,外扩DDR2 SDRAM进行数据缓存;千兆以太网电路主要以1000Mbps的速率实现与上位机的数据交互;ADC时钟电路提供ADC芯片所需的高频、高精度采样时钟;电源模块主要是为高速数据采集系统提供所需要的电源。2.进行高速数据采集系统硬件电路设计。从MALDI-TOF-MS所要检测的离子脉冲宽度、测量精度、最大质量数、叠加次数等参数确定高速数据采集系统采样率为2Gsps、分辨率为12bit、离子脉冲信号有效带宽在400MHz以内、存储容量为512MB,并通过千兆以太网口实现采样数据的批量上传。为提高采样时钟频率精度,通过选取锁相环芯片,生成ADC芯片所需要的1GHz差分时钟;调理电路模块所选芯片为具有超低噪声和超低失真的运算放大器AD8099,以及高带宽差分放大器等实现高带宽、高信噪比,且满足ADC满量程的输出信号。为保证高速信号完整性,在电路布线与PCB制板时采取了如下具体措施:(1)对于高频模拟信号和数字信号传输线,采用差分处理,有效降低噪声,提高抗干扰能力;(2)在设计电路板时采用8层制板,即顶层-地层-信号层-电源层-地层-信号层-电源层-底层,使信号层与地层或电源层相邻,保证信号返回路径阻抗最小;(3)AD模块采用100欧姆差分电阻进行阻抗匹配,减小信号反射;(4)电源层、地层布线与信号布线的走线方向一致,减小噪声干扰;(5)DDR2SDRAM模块采用蛇形走线,保持信号长度一致,满足信号时序要求;(6)信号线间距采用3W原则,减小信号间串扰;(7)表层与底层做铺地处理,以及为板卡制作法拉第电笼等,减小电磁干扰。通过以上措施,有效保证了信号完整性。3.FPGA逻辑设计。FPGA内部逻辑设计主要包括ADC时钟模块控制逻辑、ADC高速输出数据接口、DDR2 SDRAM控制器及其控制逻辑、千兆以太网芯片控制逻辑等。其中ADC时钟模块控制逻辑使FPGA芯片通过SPI接口控制锁相环芯片生成1GHz时钟,作为ADC芯片的采样时钟;ADC高速数据输出接口主要在FPGA内部例化一个输入为48bit,输出为32bit的异步FIFO,进行数据位数转换。DDR2 SDRAM控制器及其控制逻辑主要调用DDR2 SDRAM Controller with altmemphy IP核,通过控制逻辑控制IP核从而实现对DDR2 SDRAM的读写操作。千兆以太网控制逻辑主要编写了UDP协议通过GMII接口实现数据的传输。通过FPGA逻辑控制,实现了高速数据采集系统时序和控制的协调统一。4.高速数据采集系统性能测试。锁相环模块、ADC模块、存储模块和千兆以太网模块是高速数据采集系统的核心部分,分别测试高速数据采集系统的信号采集、数据存储和数据传输功能,具体结果包括:(1)以FPGA作为主控芯片,配合采样率为2Gsps、分辨率为12bit的ADC芯片对高频离子脉冲信号进行高速高精度采样。通过对250MHz输入信号进行实际采样测试,达到SNR=44.6639,ENOB=7.1269,满足设计要求;(2)以FPGA作为主控芯片,配合DDR2 SDRAM大容量存储芯片对ADC采样数据进行高速实时存储,在传输速率为667Mbps下,传输数据准确;(3)以FPGA作为主控芯片,配合千兆以太网接口实现对DDR2SDRAM中批量数据的高速上传,在传输为1000Mbps下,传输数据准确。此外,针对调理电路进行测试,实现了有效带宽在400MHz以内,且达到ADC芯片的满量程输入信号,且信噪比较高,满足设计要求。最后,对高速数据采集系统所涉及的研究工作进行了总结。本论文主要依据MALDI-TOF-MS的指标要求对数据采集系统进行需求分析和具体设计,并对高速数据采集系统板卡的核心功能和关键指标进行了测试验证,测试结果满足设计要求。下一步研究计划:1、通过完善硬件电路、软件滤波等措施,进一步提高调理电路和ADC采样电路的信噪比,实现系统测量精度和测量灵敏度的进一步提升。2、对已完成过的独立逻辑设计进行整合,实现高速数据采集系统从离子脉冲信号采集→数据存储→数据传输的完整流程,为后续进行数据处理分析并生成质谱图提供关键支撑。3、开发上位机数据解析处理算法,进一步提高测量信号精度。4、在质谱仪仿真平台上,开展高速数据采集系统的应用测试评价。
[Abstract]:Biosafety refers to the direct or potential threat to humans, animals or plants caused by biological vector through direct infection or indirect destruction of the environment. It has been found that most of the vector is caused by microorganisms. Only by quickly identifying the types and sources of microorganisms can effective measures be taken to inhibit the spread and development of infectious media. Therefore, safe, reliable, rapid and accurate microbial detection technology is one of the key problems in the field of biosafety. Biomass spectrometry based on microbial expression profiles, which is used abroad, can identify, classify, trace and monitor microorganisms quickly and accurately in the field. It has incomparable advantages over traditional microbial detection techniques, and provides a powerful analytical and testing means for Biosafety and other fields. However, it has adopted a core in China. Therefore, the development of innovative microbial detection equipment with core independent intellectual property rights and supporting technical systems has become an important issue in the field of biosafety in China. Matrix-assisted laser analytical ionization/time-of-flight mass spectrometry (MALDI-TOF-MS) is a new type of soft ionization mass spectrometry developed rapidly in recent years. It has the characteristics of high sensitivity, high accuracy and high resolution. Ion beam high-speed acquisition includes ion detector and high-speed data acquisition system, in which high-speed data acquisition system completes the data acquisition, transmission, processing and analysis of the ion pulse signal output by the detector. The measurement of high frequency weak ion pulse signal includes weak signal conditioning circuit, high speed ADC data acquisition, data storage, data upload processing and analysis. In order to improve the measurement accuracy of ion pulse signal, this paper uses FPGA as the main control chip and over sampling technology. To improve the signal-to-noise ratio, the ADC sampling rate is set to 2 Gsps, and the ADC resolution is set to 12 bits, and the corresponding storage capacity and high-speed transmission interface are expanded with the data acquisition and transmission to achieve rapid and high-precision measurement of the ion pulse signal. The specific research contents of this paper include: 1. High-speed data acquisition system design. In order to detect the ion pulse signal in TOF-MS, the hardware structure of the high-speed data acquisition system is firstly determined. The hardware circuit mainly includes the main control circuit of FPGA, signal conditioning circuit, ADC sampling circuit, DDR2 SDRAM storage circuit, Gigabit Ethernet circuit, ADC clock circuit and the power supply circuit needed. The logic control of the whole high-speed data acquisition system is realized; the signal conditioning circuit mainly converts the ionic pulse signal with the maximum output amplitude of 10 mA from MALDI-TOF-MS detector into a current-switching voltage, amplifies the weak signal, and converts the signal from single-ended output to differential output in conjunction with the ADC input mode; the high-speed ADC module converts the modulation output. The DDR2 SDRAM storage circuit realizes the caching of the sampled data and reduces the real-time transmission rate of the data. In order to improve the signal-to-noise ratio (SNR) of the ionic pulse signal measured by the sampled sample, it is necessary to sample the multiple ionic pulse signal of the same sample and superimpose the data after sampling. When the internal storage space of PGA is not enough, the external DDR2 SDRAM is used to buffer the data; the Gigabit Ethernet circuit mainly interacts with the host computer at 1000Mbps speed; the ADC clock circuit provides the high frequency and high precision sampling clock needed by the ADC chip; and the power module mainly provides the power needed for the high-speed data acquisition system. 2. Design the hardware circuit of the high-speed data acquisition system. The sampling rate of the high-speed data acquisition system is 2Gsps, the resolution is 12bit, the effective bandwidth of the ion pulse signal is within 400MHz, the storage capacity is 512MB, and the sampling rate is determined by the parameters of MALDI-TOF-MS. In order to improve the precision of sampling clock frequency, a phase-locked loop chip is selected to generate the 1GHz differential clock needed by ADC chip; the chip selected by the conditioning circuit module is an operational amplifier AD8099 with ultra-low noise and ultra-low distortion, and a high bandwidth differential amplifier. In order to ensure the integrity of high-speed signal, the following specific measures are taken in circuit wiring and PCB board making: (1) For high-frequency analog signal and digital signal transmission line, differential processing is used to effectively reduce noise and improve anti-interference ability; (2) Eight-layer board is used in circuit board design, that is, top-to-ground board. Layer-Signal Layer-Power Layer-Stratum-Signal Layer-Power Layer-Bottom Layer, so that the signal layer adjacent to the stratum or power layer, to ensure that the signal return path impedance is the smallest; (3) AD module using 100 ohm differential resistance impedance matching to reduce signal reflection; (4) power layer, stratum wiring and signal wiring alignment, reduce noise interference; (5) DDR2 SDRAM module adopts snake-like line to keep the length of signal consistent to meet the requirements of signal timing; (6) signal line spacing adopts the principle of 3W to reduce cross-talk between signals; (7) surface and bottom layers to do ground processing, as well as for the board card Faraday cage to reduce electromagnetic interference. Through the above measures, effectively ensure the integrity of the signal. 3. FPGA logic design. GA internal logic design mainly includes ADC clock module control logic, ADC high-speed output data interface, DDR2 SDRAM controller and its control logic, Gigabit Ethernet chip control logic and so on. The DDR2 SDRAM controller and its control logic call the DDR2 SDRAM Controller with altmemphy IP core, and control the IP core through the control logic to realize the read-write operation of DDR2 SDRAM. Gigabit Ethernet The control logic mainly compiles UDP protocol to realize data transmission through GMII interface. The timing and control of high-speed data acquisition system are coordinated and unified by FPGA logic control. 4. Performance test of high-speed data acquisition system. Phase-locked loop module, ADC module, storage module and Gigabit Ethernet module are the core of high-speed data acquisition system. In this part, the functions of signal acquisition, data storage and data transmission of high-speed data acquisition system are tested respectively. The specific results include: (1) High-speed and high-precision sampling of high-frequency ion pulse signal is carried out by using FPGA as the main control chip, cooperating with ADC chip with sampling rate of 2 Gsps and resolution of 12 bits. Trial, to achieve SNR = 44.6639, ENOB = 7.1269, to meet the design requirements; (2) FPGA as the main control chip, with DDR2 SDRAM large-capacity memory chip for high-speed real-time storage of ADC sampling data, in the transmission rate of 667 Mbps, accurate data transmission; (3) FPGA as the main control chip, with Gigabit Ethernet interface to achieve the DDR2 SDRAM batch data In addition, the effective bandwidth is within 400 MHz, and the full range input signal of ADC chip is achieved. The signal-to-noise ratio is high, which meets the design requirements. Finally, the research work of high-speed data acquisition system is summarized. According to the requirements of MALDI-TOF-MS, the data acquisition system is analyzed and designed, and the core functions and key indicators of the high-speed data acquisition system board are tested and verified. The test results meet the design requirements. The next research plan: 1. By improving the hardware circuit, software filtering and other measures to further improve The signal-to-noise ratio of conditioning circuit and ADC sampling circuit can further improve the measurement accuracy and sensitivity of the system. 2. Integrate the independent logic design which has been completed, realize the complete flow of high-speed data acquisition system from ion pulse signal acquisition to data storage to data transmission, and then carry on data processing and analysis for the follow-up. Mass spectrogram provides the key support. 3. Develop the upper computer data analysis and processing algorithm to further improve the measurement signal accuracy. 4. Develop the application test and evaluation of high-speed data acquisition system on the mass spectrometer simulation platform.
【学位授予单位】：中国人民解放军军事医学科学院
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TH744.5
本文编号：2176201
[Abstract]:Biosafety refers to the direct or potential threat to humans, animals or plants caused by biological vector through direct infection or indirect destruction of the environment. It has been found that most of the vector is caused by microorganisms. Only by quickly identifying the types and sources of microorganisms can effective measures be taken to inhibit the spread and development of infectious media. Therefore, safe, reliable, rapid and accurate microbial detection technology is one of the key problems in the field of biosafety. Biomass spectrometry based on microbial expression profiles, which is used abroad, can identify, classify, trace and monitor microorganisms quickly and accurately in the field. It has incomparable advantages over traditional microbial detection techniques, and provides a powerful analytical and testing means for Biosafety and other fields. However, it has adopted a core in China. Therefore, the development of innovative microbial detection equipment with core independent intellectual property rights and supporting technical systems has become an important issue in the field of biosafety in China. Matrix-assisted laser analytical ionization/time-of-flight mass spectrometry (MALDI-TOF-MS) is a new type of soft ionization mass spectrometry developed rapidly in recent years. It has the characteristics of high sensitivity, high accuracy and high resolution. Ion beam high-speed acquisition includes ion detector and high-speed data acquisition system, in which high-speed data acquisition system completes the data acquisition, transmission, processing and analysis of the ion pulse signal output by the detector. The measurement of high frequency weak ion pulse signal includes weak signal conditioning circuit, high speed ADC data acquisition, data storage, data upload processing and analysis. In order to improve the measurement accuracy of ion pulse signal, this paper uses FPGA as the main control chip and over sampling technology. To improve the signal-to-noise ratio, the ADC sampling rate is set to 2 Gsps, and the ADC resolution is set to 12 bits, and the corresponding storage capacity and high-speed transmission interface are expanded with the data acquisition and transmission to achieve rapid and high-precision measurement of the ion pulse signal. The specific research contents of this paper include: 1. High-speed data acquisition system design. In order to detect the ion pulse signal in TOF-MS, the hardware structure of the high-speed data acquisition system is firstly determined. The hardware circuit mainly includes the main control circuit of FPGA, signal conditioning circuit, ADC sampling circuit, DDR2 SDRAM storage circuit, Gigabit Ethernet circuit, ADC clock circuit and the power supply circuit needed. The logic control of the whole high-speed data acquisition system is realized; the signal conditioning circuit mainly converts the ionic pulse signal with the maximum output amplitude of 10 mA from MALDI-TOF-MS detector into a current-switching voltage, amplifies the weak signal, and converts the signal from single-ended output to differential output in conjunction with the ADC input mode; the high-speed ADC module converts the modulation output. The DDR2 SDRAM storage circuit realizes the caching of the sampled data and reduces the real-time transmission rate of the data. In order to improve the signal-to-noise ratio (SNR) of the ionic pulse signal measured by the sampled sample, it is necessary to sample the multiple ionic pulse signal of the same sample and superimpose the data after sampling. When the internal storage space of PGA is not enough, the external DDR2 SDRAM is used to buffer the data; the Gigabit Ethernet circuit mainly interacts with the host computer at 1000Mbps speed; the ADC clock circuit provides the high frequency and high precision sampling clock needed by the ADC chip; and the power module mainly provides the power needed for the high-speed data acquisition system. 2. Design the hardware circuit of the high-speed data acquisition system. The sampling rate of the high-speed data acquisition system is 2Gsps, the resolution is 12bit, the effective bandwidth of the ion pulse signal is within 400MHz, the storage capacity is 512MB, and the sampling rate is determined by the parameters of MALDI-TOF-MS. In order to improve the precision of sampling clock frequency, a phase-locked loop chip is selected to generate the 1GHz differential clock needed by ADC chip; the chip selected by the conditioning circuit module is an operational amplifier AD8099 with ultra-low noise and ultra-low distortion, and a high bandwidth differential amplifier. In order to ensure the integrity of high-speed signal, the following specific measures are taken in circuit wiring and PCB board making: (1) For high-frequency analog signal and digital signal transmission line, differential processing is used to effectively reduce noise and improve anti-interference ability; (2) Eight-layer board is used in circuit board design, that is, top-to-ground board. Layer-Signal Layer-Power Layer-Stratum-Signal Layer-Power Layer-Bottom Layer, so that the signal layer adjacent to the stratum or power layer, to ensure that the signal return path impedance is the smallest; (3) AD module using 100 ohm differential resistance impedance matching to reduce signal reflection; (4) power layer, stratum wiring and signal wiring alignment, reduce noise interference; (5) DDR2 SDRAM module adopts snake-like line to keep the length of signal consistent to meet the requirements of signal timing; (6) signal line spacing adopts the principle of 3W to reduce cross-talk between signals; (7) surface and bottom layers to do ground processing, as well as for the board card Faraday cage to reduce electromagnetic interference. Through the above measures, effectively ensure the integrity of the signal. 3. FPGA logic design. GA internal logic design mainly includes ADC clock module control logic, ADC high-speed output data interface, DDR2 SDRAM controller and its control logic, Gigabit Ethernet chip control logic and so on. The DDR2 SDRAM controller and its control logic call the DDR2 SDRAM Controller with altmemphy IP core, and control the IP core through the control logic to realize the read-write operation of DDR2 SDRAM. Gigabit Ethernet The control logic mainly compiles UDP protocol to realize data transmission through GMII interface. The timing and control of high-speed data acquisition system are coordinated and unified by FPGA logic control. 4. Performance test of high-speed data acquisition system. Phase-locked loop module, ADC module, storage module and Gigabit Ethernet module are the core of high-speed data acquisition system. In this part, the functions of signal acquisition, data storage and data transmission of high-speed data acquisition system are tested respectively. The specific results include: (1) High-speed and high-precision sampling of high-frequency ion pulse signal is carried out by using FPGA as the main control chip, cooperating with ADC chip with sampling rate of 2 Gsps and resolution of 12 bits. Trial, to achieve SNR = 44.6639, ENOB = 7.1269, to meet the design requirements; (2) FPGA as the main control chip, with DDR2 SDRAM large-capacity memory chip for high-speed real-time storage of ADC sampling data, in the transmission rate of 667 Mbps, accurate data transmission; (3) FPGA as the main control chip, with Gigabit Ethernet interface to achieve the DDR2 SDRAM batch data In addition, the effective bandwidth is within 400 MHz, and the full range input signal of ADC chip is achieved. The signal-to-noise ratio is high, which meets the design requirements. Finally, the research work of high-speed data acquisition system is summarized. According to the requirements of MALDI-TOF-MS, the data acquisition system is analyzed and designed, and the core functions and key indicators of the high-speed data acquisition system board are tested and verified. The test results meet the design requirements. The next research plan: 1. By improving the hardware circuit, software filtering and other measures to further improve The signal-to-noise ratio of conditioning circuit and ADC sampling circuit can further improve the measurement accuracy and sensitivity of the system. 2. Integrate the independent logic design which has been completed, realize the complete flow of high-speed data acquisition system from ion pulse signal acquisition to data storage to data transmission, and then carry on data processing and analysis for the follow-up. Mass spectrogram provides the key support. 3. Develop the upper computer data analysis and processing algorithm to further improve the measurement signal accuracy. 4. Develop the application test and evaluation of high-speed data acquisition system on the mass spectrometer simulation platform.
【学位授予单位】：中国人民解放军军事医学科学院
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TH744.5
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