面向多核阵列的高速互连结构设计与实现
发布时间：2018-08-12 12:22
【摘要】：随着集成电路密度的提高,系统中各个组件的复杂度急剧增大,为了应对不断增加的晶体管密度、更高的时钟频率、更低的功耗以及面向市场的压力,半导体行业将注意力从单芯片单处理器转移到单芯片多处理器和多芯片多处理器。目前的多处理器大多通过总线方式互联,然而,当处理单元数量增大到一定规模后,系统设计人员在设计互联结构时可能面临前所未有的挑战,以往基于总线的设计方法由于不可避免的存在数据冲突,缺乏可扩展性和可预测性,不能满足未来多核系统在性能、功率、时序收敛和扩展性等方面的发展需求。因此设计一个高效的高速互连结构是多核处理系统设计的一个关键。论文设计了面向多核阵列的高速互联结构,并在硬件平台上进行了实现。多核阵列高速互连结构主要采用片上网络的方式进行互联,在跨越芯片和跨越板卡时我们采用高速串行接口进行数据转换,以扩展多核的规模。论文首先研究了高速互连接口,介绍了高速互连接口中的几个核心技术,如串并转换、数据编码、时钟恢复、数据同步等,并基于硬件平台利用IBERT给出了测试Xilinx高速接口的步骤和测试结果,结果表明高速串行通道的误码率优于8 E-14,同时给出了自定协议测试和SRIO协议测试结果,测试通过。接着研究了NoC,对比了路由协议、交换结构、可靠性等核心部件,选择了性能和实现复杂度折中的方案,并给出了对应的硬件设计方案,从NI设计到路由器设计,从帧格式定义缓存大小的计算。然后给出了片内NoC和片间高速串行通道互联的实现方案,并利用SRIO通道和光通道拉通了PC和FPGA之间的双向通道,实现了数据的采集和分发,并在硬件平台上拉通了整个设计。基于设计出的多核平台,将LTE-A无线通信系统基站侧的基带处理映射到多核平台上,并完成了CoMP测试,最后基于32核的矢量处理器系统,测试了交换能力,结果表明搭建的系统达到项目指标要求。
[Abstract]:With the increasing density of integrated circuits, the complexity of each component in the system increases dramatically. In order to cope with the increasing density of transistors, higher clock frequency, lower power consumption and market-oriented pressure, The semiconductor industry shifts attention from single-chip single-processor to single-chip multi-processor and multi-chip multi-processor. At present, most multiprocessors are interconnected by bus. However, when the number of processing units increases to a certain scale, system designers may face unprecedented challenges in designing interconnected structures. Because of the inevitable data conflict and the lack of scalability and predictability, the previous design methods based on bus can not meet the development needs of future multi-core systems in terms of performance, power, timing convergence and scalability. Therefore, the design of an efficient high-speed interconnection structure is a key to the design of multi-core processing system. A high-speed interconnection architecture for multi-core array is designed and implemented on the hardware platform. Multi-core array high speed interconnection architecture mainly uses the mode of on-chip network to interconnect. In order to expand the scale of multi-core, we use high-speed serial interface for data conversion when we span chips and boards. This paper first studies the high speed interconnect interface, and introduces several core technologies in the high speed interconnection interface, such as serial-parallel conversion, data coding, clock recovery, data synchronization and so on. Based on the hardware platform, the steps and test results of testing Xilinx high-speed interface are given by using IBERT. The results show that the bit error rate of high-speed serial channel is better than that of 8E-14. Meanwhile, the test results of self-determined protocol and SRIO protocol are given, and the test results are passed. Then the paper studies Noc, compares the core components such as routing protocol, switching structure, reliability and so on, selects the compromise scheme of performance and implementation complexity, and gives the corresponding hardware design scheme, from NI design to router design. The calculation of the cache size defined from the frame format. Then, the scheme of interconnecting NoC and high-speed serial channels between chips is given, and the two-way channel between PC and FPGA is pulled through by using SRIO channel and optical channel. The data collection and distribution are realized, and the whole design is pulled through on the hardware platform. Based on the designed multi-core platform, the baseband processing of the base station side of LTE-A wireless communication system is mapped to the multi-core platform, and the CoMP test is completed. Finally, the switching ability is tested based on the 32-core vector processor system. The results show that the system meets the project requirements.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TN402
本文编号：2179042
[Abstract]:With the increasing density of integrated circuits, the complexity of each component in the system increases dramatically. In order to cope with the increasing density of transistors, higher clock frequency, lower power consumption and market-oriented pressure, The semiconductor industry shifts attention from single-chip single-processor to single-chip multi-processor and multi-chip multi-processor. At present, most multiprocessors are interconnected by bus. However, when the number of processing units increases to a certain scale, system designers may face unprecedented challenges in designing interconnected structures. Because of the inevitable data conflict and the lack of scalability and predictability, the previous design methods based on bus can not meet the development needs of future multi-core systems in terms of performance, power, timing convergence and scalability. Therefore, the design of an efficient high-speed interconnection structure is a key to the design of multi-core processing system. A high-speed interconnection architecture for multi-core array is designed and implemented on the hardware platform. Multi-core array high speed interconnection architecture mainly uses the mode of on-chip network to interconnect. In order to expand the scale of multi-core, we use high-speed serial interface for data conversion when we span chips and boards. This paper first studies the high speed interconnect interface, and introduces several core technologies in the high speed interconnection interface, such as serial-parallel conversion, data coding, clock recovery, data synchronization and so on. Based on the hardware platform, the steps and test results of testing Xilinx high-speed interface are given by using IBERT. The results show that the bit error rate of high-speed serial channel is better than that of 8E-14. Meanwhile, the test results of self-determined protocol and SRIO protocol are given, and the test results are passed. Then the paper studies Noc, compares the core components such as routing protocol, switching structure, reliability and so on, selects the compromise scheme of performance and implementation complexity, and gives the corresponding hardware design scheme, from NI design to router design. The calculation of the cache size defined from the frame format. Then, the scheme of interconnecting NoC and high-speed serial channels between chips is given, and the two-way channel between PC and FPGA is pulled through by using SRIO channel and optical channel. The data collection and distribution are realized, and the whole design is pulled through on the hardware platform. Based on the designed multi-core platform, the baseband processing of the base station side of LTE-A wireless communication system is mapped to the multi-core platform, and the CoMP test is completed. Finally, the switching ability is tested based on the 32-core vector processor system. The results show that the system meets the project requirements.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TN402
【参考文献】
相关期刊论文 前1条
1 陈书明;万江华;鲁建壮;刘仲;孙海燕;孙永节;刘衡竹;刘祥远;李振涛;徐毅;陈小文;;YHFT-QDSP:High-Performance Heterogeneous Multi-Core DSP[J];Journal of Computer Science & Technology;2010年02期
，本文编号：2179042
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