40nm MOSFET版图邻近效应模型的研究和建立

发布时间：2018-08-12 12:25

【摘要】：随着工艺技术不断创新,集成电路核心器件MOSFET的特征尺寸已缩小到深纳米量级,器件和集成芯片的性能都得到大幅提升。然而,深纳米工艺代精细的版图布局引入各类邻近效应,深纳米MOSFET器件性能因此产生波动,导致集成芯片的性能参数误差及可靠性隐患。精确的MOSFET器件模型是集成电路设计和工艺之间的桥梁,目前国内MOSFET版图邻近效应模型的缺失为降低电路设计仿真误差带来难度。因此,建立准确表征版图邻近效应的MOSFET器件模型,对深纳米工艺代中各类邻近效应做出精准描述和预测,对器件制造和电路仿真都有着重要的意义。本文首先从亚波长光刻、应力邻近、高能离子注入和瞬态增强扩散效应四个方面,分析了版图邻近效应的产生机理,研究确定了该效应对器件性能的影响主要表现在阈值电压Vth和相关电流的波动,因此选用紧凑模型委员会(CMC)认证的基于阈值电压的紧凑模型BSIM4.5作为核心模型,并对其扩展实现版图邻近模型。本文基于国有先进的40nm 1.1V MOSFET工艺平台,对从长沟至短沟的130个NMOSFET和PMOSFET进行流片和电学性能测试,完成了基于BSIM4.5的MOSFET C-V、I-V核心模型参数提取工作。MOSFET核心模型的提取结果表明,平均误差小于2%,最大误差小于5%,符合业界模型提取的标准。由于BSIM4.5模型涉及的版图邻近因子不全面,本文在MOSFET核心模型提取的基础上,结合40nm MOSFET工艺的精细版图,对STI应力邻近因子、阱邻近因子、有源区邻近因子和栅极邻近因子这四类版图邻近因子,分别建立版图邻近子模型。在版图邻近子模型中,本文着重考虑11个版图邻近因子,新添加KSODXU0、 KSODXVTH0等28个模型参数以建立40nm MOSFET器件性能波动与不同版图邻近因子相关性的物理表达式。通过对MOSFET核心模型中阈值电压表达式Vth和迁移率表达式μeff的修正,将版图邻近子模型移植到MOSFET核心模型上,完成了版图邻近效应模型的建立。为了对建立的版图邻近效应模型进行验证,本文通过对392个NMOSFET和PMOSFET测试结构的参数测试和模型比对,有效涵盖大尺寸、短沟道、窄沟道和小尺寸器件,表明本文建立的版图邻近效应模型实现了MOSFET 1-1mV的阈值电压变化量和0.5-4.5%的漏电流变化率的模拟,有效降低电路设计中的仿真误差。本文建立的40nm MOSFET版图邻近效应模型能够准确拟合MOSFET的电学性能,具有较好的可读性和可移植性,可实现更精准的电路设计和性能仿真预测。
[Abstract]:With the continuous innovation of process technology, the characteristic size of integrated circuit core device (MOSFET) has been reduced to deep nanoscale order, and the performance of device and integrated chip has been greatly improved. However, various proximity effects are introduced into the precise layout of deep nanotechnology, which leads to the fluctuation of the performance of deep nanometer MOSFET devices, which leads to the error of performance parameters and the hidden trouble of reliability of the integrated chip. Accurate MOSFET device model is a bridge between integrated circuit design and process. At present, the lack of proximity effect model of MOSFET layout makes it difficult to reduce the circuit design simulation error. Therefore, it is of great significance for device manufacturing and circuit simulation to establish an accurate MOSFET device model to describe and predict all kinds of proximity effects in deep nanotechnology. In this paper, the mechanism of the proximity effect is analyzed from four aspects: subwavelength lithography, stress proximity, high energy ion implantation and transient enhanced diffusion. It is determined that the effect of this effect on the device performance is mainly due to the fluctuation of threshold voltage (Vth) and associated current. Therefore, a compact model based on threshold voltage (BSIM4.5), which is certified by the Compact Model Committee (CMC), is chosen as the core model. And the expansion of the layout of the adjacent model. Based on the state owned advanced 40nm 1.1 V MOSFET process platform, 130 NMOSFET and PMOSFET from long ditch to short ditch were tested for flow sheet and electrical properties. The extraction results of MOSFET C-V I-V core model based on BSIM4.5. The average error is less than 2 and the maximum error is less than 5. Because the proximity factor of BSIM4.5 model is not comprehensive, based on the extraction of MOSFET core model and the fine layout of 40nm MOSFET process, the STI stress proximity factor and well proximity factor are studied. The proximity factor of active region and the proximity factor of grid are four kinds of proximity factors of layout, and the adjacent submodels of layout are established respectively. In this paper, we focus on the consideration of 11 layout proximity factors and 28 model parameters, such as KSODXU0, KSODXVTH0, etc., in order to establish the physical expression of the correlation between the performance fluctuation of 40nm MOSFET devices and the adjacent factors of different layouts. By modifying the threshold voltage expression Vth and the mobility expression 渭 eff in the MOSFET core model, the layout proximity submodel is transplanted to the MOSFET core model, and the layout proximity effect model is established. In order to verify the layout proximity effect model, through the parameter test and model comparison of 392 NMOSFET and PMOSFET test structures, this paper effectively covers large size, short channel, narrow channel and small size devices. It is shown that the proposed layout proximity effect model can simulate the threshold voltage variation of MOSFET 1-1mV and the leakage current change rate of 0.5-4.5%, which can effectively reduce the simulation error in circuit design. The proximity effect model of 40nm MOSFET layout established in this paper can accurately fit the electrical properties of MOSFET. It has better readability and portability, and can realize more accurate circuit design and performance simulation prediction.
【学位授予单位】：华东师范大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN386

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