低功耗复合逻辑门设计
发布时间：2018-08-13 15:07
【摘要】：随着半导体工艺进入深亚微米阶段以及CMOS集成电路技术的发展,集成电路的工作频率和集成度不断提高,功耗问题日益演变成超大规模电路设计的瓶颈。在集成电路设计中,复杂的逻辑功能可以通过调用逻辑门来实现。但研究发现,如将多个基本门组合产生的逻辑功能由单个复合门来替换往往可以实现电路性能的提升。这些复合门可以根据其逻辑功能,重新从晶体管级进行设计,运用多种设计方法,从而达到减小面积和改善功能的目的。本论文重点研究了低功耗的复合门电路设计,并对其在现实环境下的性能进行了详尽的阐述以及结果的对比分析。论文的研究工作主要包含了以下三个部分:1.对具有传统布尔逻辑(Traditional Boolean,TB)的复合逻辑门设计的讨论。针对目前布尔逻辑大多只利用了基础单元的“与非”、“非”和“或非”等逻辑的单元电路来实现大规模电路的设计,这样的设计虽然取用单元电路方便,但也存在取用的单元电路数量多,面积大的缺陷。与传统的单元电路级联而成的基于TB逻辑复合门电路相比,基于晶体管级设计的电路拥有更小的面积和功耗。2.具有Reed-Muller(RM)逻辑的复合逻辑门单元电路的设计研究。针对现有RM逻辑,如三输入“或/同或”,“异或/与”,在集成电路中以两个二输入门电路级联形式出现,导致功耗大、延时长的不足,提出一种基于晶体管级复合逻辑门电路结构的设计方案。该电路通过采用多轨结构、缩短传输路径,以及混合CMOS逻辑等设计方法,来克服原有电路中单一逻辑和单轨结构信号路径长的不足,进而提高电路性能。在55nm的CMOS技术工艺和PTM多种工艺下,经过HSPICE模拟和Cadence提取版图的后仿真,所设计的电路具有正确的逻辑功能,相较于采用门电路级联而成的复合门电路,在不同负载、频率和PVT组合等情况下的延时、功耗和功耗延迟积(PDP)都得到了明显的改善。3.电路性能的测试环境设置及测量方法。在一些电路的性能比较中,设计者给出的测试方法往往并不能全面地反映电路的性能。本文在研究各电路的比较方式和方法后,提出给出一种相对公平的电路测试参考方案。
[Abstract]:With the development of semiconductor technology in deep submicron stage and CMOS integrated circuit technology, the working frequency and integration level of integrated circuit are increasing, and the power consumption problem is becoming the bottleneck of very large scale circuit design day by day. In integrated circuit design, complex logic function can be realized by calling logic gate. However, it is found that if the logic function generated by the combination of multiple basic gates is replaced by a single composite gate, the performance of the circuit can be improved. These composite gates can be redesigned from the transistor level according to their logic functions, and various design methods can be used to reduce the area and improve the function. This paper focuses on the design of low power compound gate circuit, and gives a detailed description of its performance in the real environment and a comparative analysis of the results. The research work of this paper mainly includes the following three parts: 1. The design of composite logic gates with traditional Boolean logic (Traditional Boolean terabytes) is discussed. At present, most Boolean logic uses only the cell circuits of the basic unit such as "and not", "not" and "or not" to realize the design of large-scale circuits. However, there are many cell circuits and large area defects. Compared with the traditional circuit cascaded based on TB logic gate, the transistor level circuit has a smaller area and power consumption. Research on the Design of compound Logic Gate Circuit with Reed-Muller (RM) Logic. For existing RM logic, such as three-input "or / or", "XOR / and", in the integrated circuit as two two-input gate circuit cascaded form, resulting in high power consumption, long delay, A design scheme based on transistor-level compound logic gate structure is presented. The circuit adopts multi-track structure, shortens the transmission path, and uses mixed CMOS logic to overcome the shortcomings of single logic and monorail structure signal path length in the original circuit, thereby improving the circuit performance. Under the CMOS technology and PTM technology of 55nm, after HSPICE simulation and post-simulation of Cadence extraction layout, the designed circuit has the correct logic function, compared with the composite gate circuit which is cascaded by gate circuit, it is under different loads. In the case of frequency and PVT combination, delay, power consumption and power delay product (PDP) are significantly improved. 3. Setting up test environment and measuring method of circuit performance. In the performance comparison of some circuits, the test methods given by the designers often do not reflect the performance of the circuits comprehensively. After studying the comparison methods of each circuit, a relatively fair circuit test reference scheme is proposed in this paper.
【学位授予单位】：宁波大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN791
[Abstract]:With the development of semiconductor technology in deep submicron stage and CMOS integrated circuit technology, the working frequency and integration level of integrated circuit are increasing, and the power consumption problem is becoming the bottleneck of very large scale circuit design day by day. In integrated circuit design, complex logic function can be realized by calling logic gate. However, it is found that if the logic function generated by the combination of multiple basic gates is replaced by a single composite gate, the performance of the circuit can be improved. These composite gates can be redesigned from the transistor level according to their logic functions, and various design methods can be used to reduce the area and improve the function. This paper focuses on the design of low power compound gate circuit, and gives a detailed description of its performance in the real environment and a comparative analysis of the results. The research work of this paper mainly includes the following three parts: 1. The design of composite logic gates with traditional Boolean logic (Traditional Boolean terabytes) is discussed. At present, most Boolean logic uses only the cell circuits of the basic unit such as "and not", "not" and "or not" to realize the design of large-scale circuits. However, there are many cell circuits and large area defects. Compared with the traditional circuit cascaded based on TB logic gate, the transistor level circuit has a smaller area and power consumption. Research on the Design of compound Logic Gate Circuit with Reed-Muller (RM) Logic. For existing RM logic, such as three-input "or / or", "XOR / and", in the integrated circuit as two two-input gate circuit cascaded form, resulting in high power consumption, long delay, A design scheme based on transistor-level compound logic gate structure is presented. The circuit adopts multi-track structure, shortens the transmission path, and uses mixed CMOS logic to overcome the shortcomings of single logic and monorail structure signal path length in the original circuit, thereby improving the circuit performance. Under the CMOS technology and PTM technology of 55nm, after HSPICE simulation and post-simulation of Cadence extraction layout, the designed circuit has the correct logic function, compared with the composite gate circuit which is cascaded by gate circuit, it is under different loads. In the case of frequency and PVT combination, delay, power consumption and power delay product (PDP) are significantly improved. 3. Setting up test environment and measuring method of circuit performance. In the performance comparison of some circuits, the test methods given by the designers often do not reflect the performance of the circuits comprehensively. After studying the comparison methods of each circuit, a relatively fair circuit test reference scheme is proposed in this paper.
【学位授予单位】：宁波大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN791
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1 张顺兴;CMOS集成逻辑门的线性应用[J];江苏通信技术;1996年S1期
2 马晓宇;浅谈基本逻辑门的综合分析与对照[J];内蒙古科技与经济;2005年20期
3 朱卫华;;分子逻辑门[J];山西大同大学学报(自然科学版);2008年01期
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5 秋小强;杨海钢;周发标;谢元禄;;非线性延时模型及逻辑门优化设计[J];微电子学;2011年06期
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