高压互连结构研究与设计
发布时间：2018-08-13 15:14
【摘要】：高压互连(HVI)是功率集成电路(PIC)中的重要技术,随着PIC在结构功能上的发展和应用范围上的增大,人们对功率集成电路中的高压互连技术的要求也与日俱增。本文围绕高压互连技术进行研究,重点研究高压互连技术和Divided RESURF结构。主要研究内容如下:1、通过建立模型研究了高压互连线对器件的影响,并总结了包括厚绝缘层技术、降场层技术、场板技术。厚绝缘层技术增加了HVI与硅表面之间的距离;降场层技术引入了额外的经过优化的掺杂区域来辅助HVI下方的漂移区的耗尽。场板技术通过多种多样的场板结构来屏蔽HVI的影响。自屏蔽技术让HVI避免跨过高压结终端,从而不再需要额外的隔离结构。2、通过仿真探究互连线对RESURF器件的影响因素,并根据仿真结果设计了包括:一种窄线宽的高压互连结构、一种部分场板屏蔽的高压互连结构、一种多片式高压互连结构等新型高压互连结构。3、使用Divided RESURF技术设计一种横向双扩散金属氧化物半导体场效应晶体管(LDMOS),通过进行二维工艺仿真,优化其结构和掺杂浓度等参数,器件的击穿耐压达到818V,可用于600V的电平位移电路中。
[Abstract]:High voltage interconnection (HVI) is an important technology in power integrated circuit (PIC). With the development and application of PIC in structure and function, the demand for high voltage interconnection in power integrated circuit is increasing. This paper focuses on high-voltage interconnection technology and Divided RESURF structure. The main research contents are as follows: 1. The influence of high voltage interconnection on the device is studied by establishing a model, and including thick insulating layer technology, falling field layer technology and field board technology. Thick insulating layer technology increases the distance between HVI and silicon surface, and down-field layer technique introduces additional optimized doping regions to assist the depletion of drift regions beneath HVI. Field plate technology shields the influence of HVI through a variety of field plate structures. Self-shielding technology allows HVI to avoid crossing the high-voltage junction terminal, thus eliminating the need for additional isolation structure .2. the influence factors of interconnection on RESURF devices are explored through simulation. According to the simulation results, a high-voltage interconnection structure with narrow linewidth is designed. A high voltage interconnection structure with partial field board shielding, A new type of high voltage interconnection structure such as multichip high voltage interconnection. Using Divided RESURF technology, a transverse double diffusion metal oxide semiconductor field effect transistor (LDMOS),) is designed and its structure and doping concentration are optimized by two dimensional process simulation. The breakdown voltage of the device is 818 V, which can be used in 600 V level displacement circuit.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN402
[Abstract]:High voltage interconnection (HVI) is an important technology in power integrated circuit (PIC). With the development and application of PIC in structure and function, the demand for high voltage interconnection in power integrated circuit is increasing. This paper focuses on high-voltage interconnection technology and Divided RESURF structure. The main research contents are as follows: 1. The influence of high voltage interconnection on the device is studied by establishing a model, and including thick insulating layer technology, falling field layer technology and field board technology. Thick insulating layer technology increases the distance between HVI and silicon surface, and down-field layer technique introduces additional optimized doping regions to assist the depletion of drift regions beneath HVI. Field plate technology shields the influence of HVI through a variety of field plate structures. Self-shielding technology allows HVI to avoid crossing the high-voltage junction terminal, thus eliminating the need for additional isolation structure .2. the influence factors of interconnection on RESURF devices are explored through simulation. According to the simulation results, a high-voltage interconnection structure with narrow linewidth is designed. A high voltage interconnection structure with partial field board shielding, A new type of high voltage interconnection structure such as multichip high voltage interconnection. Using Divided RESURF technology, a transverse double diffusion metal oxide semiconductor field effect transistor (LDMOS),) is designed and its structure and doping concentration are optimized by two dimensional process simulation. The breakdown voltage of the device is 818 V, which can be used in 600 V level displacement circuit.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN402
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