流水线ADC数字后台校准方法研究

发布时间：2018-08-19 07:41

【摘要】：现代电子技术的进步带动了对高性能模数转换器的需求。与其它结构模数转换器相比,流水线ADC在速度、精度、功耗等方面具有独特的优势,是近年来模数转换器设计研究领域的重点之一。为进一步提高流水线ADC的性能,在传统模拟电路设计因CMOS工艺进步而逐渐遭遇瓶颈的情况下,利用数字校准技术辅助模拟电路设计正成为流水线ADC研究与设计的趋势。数字后台校准技术可以在不打断流水线ADC正常转换工作的情况下,及时动态地校准流水线ADC的误差,提高流水线ADC的性能指标。本文基于8位流水线ADC设计,分析了各类影响流水线ADC性能的误差参数,并针对最为重要的电容失配与运放有限增益引起的误差,提出了一种数字后台校准方案。该方案通过向被校准流水线级的MDAC电路注入PN序列,计算由上述两者引起的级间增益误差,修正该级数字量输出,以此来校准流水线ADC的线性及非线性误差,并通过反馈补偿的方式抵消了引入PN序列带来的额外影响。该方案经过Simulink建模验证,仿真结果表明,应用校准方案后的流水线ADC信噪失真比提高了 4dB,无杂散动态范围提高了 21dB。经验证的校准方案最终通过数字集成电路实现。采用SMIC 0.18μm 1P6M工艺,完成了 RTL级代码编写、功能仿真、FPGA验证、逻辑综合、静态时序分析、形式验证、物理版图设计及验证等工作。最终得到的数字电路版图工作频率为25MHz,芯片面积约1.5*1.5mm2,功耗小于9mW。本文提出的数字后台校准方案,达到了校准流水线ADC电容失配与运放有限增益误差的效果,提升了流水线ADC的性能指标。其电路实现面积小、功耗低,具有实际意义。
[Abstract]:The development of modern electronic technology drives the demand for high performance A / D converters. Compared with other analog-to-digital converters, pipelined ADC has unique advantages in speed, precision, power consumption and so on. It is one of the most important research fields in the design of analog-to-digital converters in recent years. In order to further improve the performance of pipelined ADC, the traditional analog circuit design has gradually encountered a bottleneck due to the progress of CMOS process. The use of digital calibration technology to assist analog circuit design is becoming the trend of pipeline ADC research and design. The digital background calibration technique can dynamically calibrate the errors of pipelined ADC without interrupting the normal conversion of pipelined ADC and improve the performance of pipeline ADC. Based on the design of 8-bit pipelined ADC, this paper analyzes the error parameters that affect the performance of pipelined ADC, and proposes a digital background calibration scheme for the errors caused by the most important capacitive mismatch and limited gain of operational amplifier. By injecting PN sequence into the calibrated pipelined MDAC circuit, the scheme calculates the inter-stage gain error caused by the above two steps, and corrects the output of the digital output of the stage to calibrate the linear and nonlinear errors of the pipelined ADC. The additional effect of introducing PN sequence is offset by feedback compensation. The simulation results show that the signal-to-noise-to-noise ratio of pipelined ADC is increased by 4dBand the non-spurious dynamic range is increased by 21dB. the simulation results show that the proposed scheme is verified by Simulink modeling. The verified calibration scheme is finally implemented by digital integrated circuit. Using SMIC 0.18 渭 m 1P6M process, the work of RTL level code writing, functional simulation and verification, logic synthesis, static timing analysis, formal verification, physical layout design and verification are completed. The final digital circuit layout frequency is 25MHz, the chip area is about 1.5mm2, and the power consumption is less than 9mW. The digital background calibration scheme proposed in this paper achieves the effect of calibration pipeline ADC capacitor mismatch and limited gain error of operational amplifier and improves the performance index of pipeline ADC. The circuit has small area and low power consumption, which is of practical significance.
【学位授予单位】：北京交通大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN792

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