GMAC桥协议转换电路的功能验证及激励自动生成方法研究
发布时间：2018-08-28 10:15
【摘要】：随着集成电路规模以及功能复杂度的快速发展,人们越来越关注集成电路功能验证的效率和可靠性。本文设计完成了FT-X DSP芯片中的GMAC桥部件,并对其功能进行了充分验证。针对总线接口类电路,提出了一种功能规范建模方法,形成了功能规范描述语言。基于所构建功能规范模型,提出了测试激励自动生成算法,并使用基于System Verilog的UVM验证方法学进行了设计实现。为所设计的GMAC桥部件搭建验证平台,并为其功能规范建模,从而自动生成测试激励,实验结果证明这种方法可以有效地提高功能验证的时间效率和功能覆盖率。本文的主要工作包括有以下五点内容:1)完成FT-X DSP芯片内部互连结构中GMAC桥的设计实现工作,对其设计方法进行总结。通过电路设计有限自动机,分析GMAC桥电路数据传输过程的控制开销,并对GMAC桥电路的数据传输效率进行了系统级环境下的实验验证,证明可以高效完成协议转换及数据传输;2)针对总线接口类电路的功能特点,对其功能规范的特点和组成成分进行研究。在此基础上,对总线接口类电路的功能属性进行分类,并对其功能特性进行抽象整合,进而建立基于功能规范的总线接口类电路功能验证方法;3)使用高阶逻辑设计功能规范描述语言,设计信号时序关系的逻辑化表达方式,并通过BNF范式建立描述语言语法规则,建立总线接口类电路功能规范点的形式化描述。基于形式化表达的集成电路功能规范点,建立功能规范模型;4)以功能规范模型为基础,设计有效测试向量的生成方法,实现总线接口类电路测试向量的生成。采用功能覆盖率驱动的方法,结合模拟退火算法思想,自动判断是否采纳测试向量为激励,产生高效的测试激励并保证验证过程的完备性;实现多个电路功能点的并行交叉验证,缓解了对多个功能点进行验证时的组合爆炸问题;使用基于System Verilog的UVM验证方法学,设计验证组件,实现测试激励自动生成算法,完成基于功能规范模型的功能验证系统设计,并完成验证系统的测试、调试工作;5)对GMAC桥电路进行功能规范建模,并搭建验证平台,进行激励自动生成的模拟验证。实验结果显示,GMAC桥电路能够实现功能规范中描述的全部功能点。当功能覆盖率达到100%时,基于功能规范模型的测试激励生成方法比传统的人工激励编写方法产生激励数量平均减少21.15%,并且激励生成所需时间大幅缩减。实验结果证明基于功能规范模型的测试激励自动生成方法能够高效完成的总线接口类电路的功能验证。
[Abstract]:With the rapid development of IC scale and functional complexity, more and more attention has been paid to the efficiency and reliability of IC functional verification. In this paper, the GMAC bridge part in FT-X DSP chip is designed and its function is fully verified. In this paper, a modeling method of function specification is proposed for bus interface circuits, and a function specification description language is formed. Based on the function specification model, an automatic generation algorithm of test excitation is proposed, and UVM verification methodology based on System Verilog is used to design and implement it. The verification platform is built for the designed GMAC bridge components, and the function specification is modeled to generate test excitation automatically. The experimental results show that this method can effectively improve the time efficiency and function coverage of function verification. The main work of this paper includes the following five points: 1) finish the design and implementation of GMAC bridge in the interconnect structure of FT-X DSP chip, and summarize its design method. Through circuit design finite automata, the control overhead of GMAC bridge circuit data transmission process is analyzed, and the data transmission efficiency of GMAC bridge circuit is verified by experiments in system level. It is proved that protocol conversion and data transmission can be accomplished efficiently. According to the functional characteristics of bus interface circuit, the characteristics and components of its function specification are studied. On this basis, the functional properties of bus interface class circuits are classified, and their functional characteristics are abstractly integrated. Furthermore, the function verification method of bus interface circuit based on function specification is established. The description language of high order logic design function specification is used to design the logical expression method of signal timing relationship, and the syntax rules of description language are established by BNF normal form. The formal description of the function specification points of bus interface circuit is established. Based on the formal representation of IC functional specification points, a functional specification model is established. Based on the functional specification model, an effective test vector generation method is designed to generate test vectors for bus interface circuits. The method of function coverage driven and simulated annealing algorithm is used to automatically judge whether the test vector is adopted as an incentive to generate efficient test incentives and ensure the completeness of the verification process. The parallel cross verification of multiple circuit function points is realized, and the combinatorial explosion problem is alleviated in the verification of multiple function points. Using UVM verification methodology based on System Verilog, the verification component is designed, and the automatic generating algorithm of test excitation is realized. The function verification system based on the function specification model is designed, and the test of the verification system is completed. The debugging work 5) builds the functional specification modeling for the GMAC bridge circuit, and builds the verification platform for the simulation verification of the excitation automatic generation. The experimental results show that the GMAC bridge circuit can realize all the function points described in the function specification. When the function coverage rate reaches 100, the test incentive generation method based on the function specification model reduces the average number of incentives generated by the traditional manual incentive writing method by 21.15, and the time required to generate the excitation is greatly reduced. The experimental results show that the automatic generation of test excitation based on the function specification model can efficiently verify the function of the bus interface class circuit.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN402
本文编号：2209092
[Abstract]:With the rapid development of IC scale and functional complexity, more and more attention has been paid to the efficiency and reliability of IC functional verification. In this paper, the GMAC bridge part in FT-X DSP chip is designed and its function is fully verified. In this paper, a modeling method of function specification is proposed for bus interface circuits, and a function specification description language is formed. Based on the function specification model, an automatic generation algorithm of test excitation is proposed, and UVM verification methodology based on System Verilog is used to design and implement it. The verification platform is built for the designed GMAC bridge components, and the function specification is modeled to generate test excitation automatically. The experimental results show that this method can effectively improve the time efficiency and function coverage of function verification. The main work of this paper includes the following five points: 1) finish the design and implementation of GMAC bridge in the interconnect structure of FT-X DSP chip, and summarize its design method. Through circuit design finite automata, the control overhead of GMAC bridge circuit data transmission process is analyzed, and the data transmission efficiency of GMAC bridge circuit is verified by experiments in system level. It is proved that protocol conversion and data transmission can be accomplished efficiently. According to the functional characteristics of bus interface circuit, the characteristics and components of its function specification are studied. On this basis, the functional properties of bus interface class circuits are classified, and their functional characteristics are abstractly integrated. Furthermore, the function verification method of bus interface circuit based on function specification is established. The description language of high order logic design function specification is used to design the logical expression method of signal timing relationship, and the syntax rules of description language are established by BNF normal form. The formal description of the function specification points of bus interface circuit is established. Based on the formal representation of IC functional specification points, a functional specification model is established. Based on the functional specification model, an effective test vector generation method is designed to generate test vectors for bus interface circuits. The method of function coverage driven and simulated annealing algorithm is used to automatically judge whether the test vector is adopted as an incentive to generate efficient test incentives and ensure the completeness of the verification process. The parallel cross verification of multiple circuit function points is realized, and the combinatorial explosion problem is alleviated in the verification of multiple function points. Using UVM verification methodology based on System Verilog, the verification component is designed, and the automatic generating algorithm of test excitation is realized. The function verification system based on the function specification model is designed, and the test of the verification system is completed. The debugging work 5) builds the functional specification modeling for the GMAC bridge circuit, and builds the verification platform for the simulation verification of the excitation automatic generation. The experimental results show that the GMAC bridge circuit can realize all the function points described in the function specification. When the function coverage rate reaches 100, the test incentive generation method based on the function specification model reduces the average number of incentives generated by the traditional manual incentive writing method by 21.15, and the time required to generate the excitation is greatly reduced. The experimental results show that the automatic generation of test excitation based on the function specification model can efficiently verify the function of the bus interface class circuit.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN402
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