SoC片上系统测试调度优化技术研究
发布时间：2018-09-01 15:23
【摘要】：随着集成电子技术的飞速发展,系统芯片(So C,System-on-a-Chip)得到越来越广泛的应用,其采用了IP核复用技术,具有集成度高、体积小、性能稳定,开发周期短等诸多优势。但是,芯片集成的功能越来越多,结构也越来越复杂,内部IP核的数量在持续增长,测试时间急剧增加。针对这些问题,有必要研究有效的测试调度方法,以实现测试时间的优化。主要研究内容有:首先,深入研究可测性设计、内建自测试、边界扫描测试、扫描测试等So C测试相关技术,提出本课题的总体研究方案。主要从测试体系结构和测试调度算法两方面展开研究与设计。从测试环和测试访问机制两方面对测试体系结构进行设计;对测试调度问题进行划分,并从减少测试时间的角度,设计IP核并行测试调度算法。其次,完成了测试体系结构的设计。使用Verilog语言对测试环的组成部分边界寄存器、旁路寄存器、指令寄存器进行了功能描述与模块封装,实现完整测试环的构建;设计了一种测试总线按位划分的测试访问机制。使用Modelsim软件对设计的结构进行仿真,验证功能正确性。然后,对比分析测试调度经典算法,提出基于改进蚁群的测试调度算法,并且应用实例,将本文的调度方法与线性规划、遗传算法进行实验结果比较,表明该算法可以缩短So C的总测试时间。最后,选用ITC’02标准测试电路d695为被测电路,对其进行可测性设计,搭建了实验平台。设计了不同TAM带宽下的实验,将本文调度方法与其他方法的实际测试时间进行对比,验证了该方法的优越性。
[Abstract]:With the rapid development of integrated electronic technology, So system on-a-Chip (So) is more and more widely used. It adopts IP core reuse technology, which has many advantages, such as high integration, small volume, stable performance, short development period and so on. However, the number of internal IP cores continues to grow and the test time increases dramatically. To solve these problems, it is necessary to study effective test scheduling methods to optimize test time. The main research contents are as follows: firstly, the related technologies of So C test, such as testability design, built-in self-test, boundary scan test and scan test, are studied deeply, and the overall research scheme of this subject is put forward. Research and design mainly from two aspects of test architecture and test scheduling algorithm. The test architecture is designed from two aspects of test loop and test access mechanism, and the test scheduling problem is partitioned, and the parallel test scheduling algorithm based on IP core is designed from the point of reducing test time. Secondly, the design of test architecture is completed. The function description and module encapsulation of the component boundary register, bypass register and instruction register of the test ring are carried out by using Verilog language, and the construction of the complete test ring is realized, and a test access mechanism of the test bus is designed. The Modelsim software is used to simulate the structure of the design to verify the correctness of the function. Then, by comparing and analyzing the classical test scheduling algorithm, a test scheduling algorithm based on improved ant colony is proposed, and the experimental results of this method are compared with that of linear programming and genetic algorithm. It shows that the algorithm can shorten the total test time of So C. Finally, the ITC'02 standard test circuit d695 is selected as the tested circuit, and the testability design is carried out, and the experimental platform is built. Experiments with different TAM bandwidth are designed and compared with the actual test time of other methods, the superiority of this method is verified.
【学位授予单位】：哈尔滨工业大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN47
本文编号：2217597
[Abstract]:With the rapid development of integrated electronic technology, So system on-a-Chip (So) is more and more widely used. It adopts IP core reuse technology, which has many advantages, such as high integration, small volume, stable performance, short development period and so on. However, the number of internal IP cores continues to grow and the test time increases dramatically. To solve these problems, it is necessary to study effective test scheduling methods to optimize test time. The main research contents are as follows: firstly, the related technologies of So C test, such as testability design, built-in self-test, boundary scan test and scan test, are studied deeply, and the overall research scheme of this subject is put forward. Research and design mainly from two aspects of test architecture and test scheduling algorithm. The test architecture is designed from two aspects of test loop and test access mechanism, and the test scheduling problem is partitioned, and the parallel test scheduling algorithm based on IP core is designed from the point of reducing test time. Secondly, the design of test architecture is completed. The function description and module encapsulation of the component boundary register, bypass register and instruction register of the test ring are carried out by using Verilog language, and the construction of the complete test ring is realized, and a test access mechanism of the test bus is designed. The Modelsim software is used to simulate the structure of the design to verify the correctness of the function. Then, by comparing and analyzing the classical test scheduling algorithm, a test scheduling algorithm based on improved ant colony is proposed, and the experimental results of this method are compared with that of linear programming and genetic algorithm. It shows that the algorithm can shorten the total test time of So C. Finally, the ITC'02 standard test circuit d695 is selected as the tested circuit, and the testability design is carried out, and the experimental platform is built. Experiments with different TAM bandwidth are designed and compared with the actual test time of other methods, the superiority of this method is verified.
【学位授予单位】：哈尔滨工业大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN47
【参考文献】
相关期刊论文 前3条
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3 雷加;方刚;;一种基于遗传算法的SoC测试调度方法[J];仪器仪表学报;2007年S1期
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