8通道Pipeline ADC的研究
发布时间：2018-09-05 14:15
【摘要】：随着无线通信技术、集成电路的快速发展,高速高精度的模数转换器,继续成为一个现代通信系统的主要构建模块。目前,在高速与高精度之间达到最好折中的模数转换器只有流水线模数转换器(Pipeline ADC)。经过长期研究,这种结构的单通道Pipeline ADC的性能在特定条件下基本达到了极限,尤其是转换速率。在这种背景下,多通道Pipeline ADC突破了单通道Pipeline ADC采样率的瓶颈。但是,通道之间的失配影响着多通道Pipeline ADC的精度。这种失配包括:失调、增益、带宽、参考电压、采样时刻等的偏差。目前,随着电子设备工作速率的提高,应用在其中的ADC的转换速率也需要提高。提高采样率的方法有两种,一种是改善工艺,另一种就是用多通道ADC并行工作来达到较高采样率,由于目前工艺已经比较先进了,因此一般采取第二种方法。当对一个模拟信号进行处理时,可以将信号通过一个多路选择器对通道进行选择,选中的通道对此刻的输入信号进行处理,多通道交替对模拟输入信号进行采样,这样就可以提高采样率。因此,本文设计了一种8通道的Pipeline ADC,此设计中子通道ADC的精度为14比特,采样率为12.5 MHz,那么8通道就可以获得100 MHz的采样率。在0.5μm CSMC CMOS的工艺条件下,根据增益、带宽、功耗、噪声等的折中考虑,确定了子通道ADC由12级1.5比特和1级2比特Flash ADC组成。其中,两相不交叠时钟分别控制奇数子级与偶数子级交替工作,各级经过延迟对准与冗余校准,最终由双端口输出14位数字信号。在8通道的Pipeline ADC的子通道ADC中,设计了关键电路模块:余量增益电路、跨导运算放大器、动态比较器、共模反馈电路和延时校准电路;在系统级电路中,设计了关键的芯片级模块:参考电压产生电路、带隙基准产生电路、偏置电流产生电路、时钟控制电路、复位电路、时钟树。并对这些模块以及整个系统进行了仿真,基本能够达到本设计的要求。最终用0.5μm CSMC CMOS工艺,三层金属,两层多晶硅流片,实现了8通道的Pipeline ADC。用Cadence软件中的Spectre工具8通道Pipeline ADC系统进行仿真,当输入信号频率为6.25 MHz时,得到性能参数有:DNL为+0.65/-0.80 LSB,INL为+0.78/-1.58 LSB,ENOB为12.06bits,SFDR为80.96 dB,SNR为74.3612 dB,达到了最初设计的要求。
[Abstract]:With the rapid development of wireless communication technology and integrated circuits, high speed and high precision analog-to-digital converters continue to be the main building blocks of a modern communication system. At present, only pipelined A / D converter (Pipeline ADC). Is the best compromise between high speed and high precision. After a long period of research, the performance of this kind of single channel Pipeline ADC has basically reached the limit under certain conditions, especially the conversion rate. In this context, multi-channel Pipeline ADC breaks through the bottleneck of single channel Pipeline ADC sampling rate. However, the mismatch between channels affects the accuracy of multichannel Pipeline ADC. This mismatch includes offset, gain, bandwidth, reference voltage, sampling time, and so on. At present, with the improvement of the working rate of electronic equipment, the conversion rate of ADC used in it also needs to be improved. There are two methods to improve the sampling rate, one is to improve the process, the other is to use multi-channel ADC to work in parallel to achieve a higher sampling rate. When an analog signal is processed, the signal can be selected through a multiplexer, the selected channel processes the input signal at the moment, and the analog input signal is sampled alternately. In this way, the sampling rate can be improved. Therefore, an 8-channel Pipeline ADC, is designed. The precision of the neutron channel ADC is 14 bits and the sampling rate is 12.5 MHz,. Then the 8-channel sampling rate of 100 MHz can be obtained. Under the condition of 0.5 渭 m CSMC CMOS, according to the trade-off among gain, bandwidth, power consumption and noise, it is determined that the sub-channel ADC consists of 12 stage 1.5 bits and 1 stage 2 bit Flash ADC. The two-phase non-overlapping clock controls the odd sub-stage and even sub-stage to work alternately. After delayed alignment and redundant calibration, 14 bit digital signals are output from two ports. In the sub-channel ADC of 8-channel Pipeline ADC, the key circuit modules are designed: residual gain circuit, transconductance operational amplifier, dynamic comparator, common-mode feedback circuit and delay calibration circuit. Key chip-level modules are designed: reference voltage generation circuit, bandgap reference generation circuit, bias current generation circuit, clock control circuit, reset circuit, clock tree. These modules and the whole system are simulated and can basically meet the requirements of this design. Finally, with 0.5 渭 m CSMC CMOS process, three layers of metal and two layers of polysilicon wafers, 8-channel Pipeline ADC. is realized. The 8-channel Pipeline ADC system with Spectre tool in Cadence software is simulated. When the input signal frequency is 6.25 MHz, the performance parameters are obtained: 0.65% -0.80 LSB,INL, 0.78% -1.58 LSB,ENOB, 12.06 bits SFDR, 80.96 dB,SNR and 74.3612 dB,.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN792
本文编号：2224533
[Abstract]:With the rapid development of wireless communication technology and integrated circuits, high speed and high precision analog-to-digital converters continue to be the main building blocks of a modern communication system. At present, only pipelined A / D converter (Pipeline ADC). Is the best compromise between high speed and high precision. After a long period of research, the performance of this kind of single channel Pipeline ADC has basically reached the limit under certain conditions, especially the conversion rate. In this context, multi-channel Pipeline ADC breaks through the bottleneck of single channel Pipeline ADC sampling rate. However, the mismatch between channels affects the accuracy of multichannel Pipeline ADC. This mismatch includes offset, gain, bandwidth, reference voltage, sampling time, and so on. At present, with the improvement of the working rate of electronic equipment, the conversion rate of ADC used in it also needs to be improved. There are two methods to improve the sampling rate, one is to improve the process, the other is to use multi-channel ADC to work in parallel to achieve a higher sampling rate. When an analog signal is processed, the signal can be selected through a multiplexer, the selected channel processes the input signal at the moment, and the analog input signal is sampled alternately. In this way, the sampling rate can be improved. Therefore, an 8-channel Pipeline ADC, is designed. The precision of the neutron channel ADC is 14 bits and the sampling rate is 12.5 MHz,. Then the 8-channel sampling rate of 100 MHz can be obtained. Under the condition of 0.5 渭 m CSMC CMOS, according to the trade-off among gain, bandwidth, power consumption and noise, it is determined that the sub-channel ADC consists of 12 stage 1.5 bits and 1 stage 2 bit Flash ADC. The two-phase non-overlapping clock controls the odd sub-stage and even sub-stage to work alternately. After delayed alignment and redundant calibration, 14 bit digital signals are output from two ports. In the sub-channel ADC of 8-channel Pipeline ADC, the key circuit modules are designed: residual gain circuit, transconductance operational amplifier, dynamic comparator, common-mode feedback circuit and delay calibration circuit. Key chip-level modules are designed: reference voltage generation circuit, bandgap reference generation circuit, bias current generation circuit, clock control circuit, reset circuit, clock tree. These modules and the whole system are simulated and can basically meet the requirements of this design. Finally, with 0.5 渭 m CSMC CMOS process, three layers of metal and two layers of polysilicon wafers, 8-channel Pipeline ADC. is realized. The 8-channel Pipeline ADC system with Spectre tool in Cadence software is simulated. When the input signal frequency is 6.25 MHz, the performance parameters are obtained: 0.65% -0.80 LSB,INL, 0.78% -1.58 LSB,ENOB, 12.06 bits SFDR, 80.96 dB,SNR and 74.3612 dB,.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN792
【参考文献】
相关硕士学位论文 前1条
1 陈雨;用于高速高精度A/D转化器的MDAC系统分析和设计[D];西安电子科技大学;2014年
，本文编号：2224533
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