应用于高清数字视频的低功耗流水线ADC的设计
发布时间：2018-09-11 10:48
【摘要】：现代电子系统的运算处理部分几乎全部实现了数字化,而在自然界中,信号基本上是以模拟的形式存在的,因而需要一个中间介质把模拟信号转化成数字信号,这个介质就是模数转换器(ADC)。ADC作为数字与模拟的桥梁得到广泛应用,特别是在数字信号处理、雷达信号分析、医疗影像设备、多媒体设备等领域。本论文是以高清数字视频显示为应用背景。高速高精度低功耗是ADC先进技术的体现和未来的发展趋势。高速高精度低功耗ADC芯片设计采用的结构比较典型的有全并行结构(flash)、流水线结构(pipeline)、逐次逼近结构(SAR)、delta-sigma型。由于pipeline ADC具有在精度、速度、面积以及功耗上折中的特点,能够很好地应用于数字通信系统、高清视频显示系统等领域。随着CMOS工艺的晶体管的特征尺寸不断缩短,晶体管的精度速度功耗等性能指标不断提高,基于传统的设计方法和结构已不能满足需求。因此,数字校正技术应运而生,可以大大提高ADC性能。本论文以高速高精度低功耗ADC为研究课题,通过对pipeline ADC的结构以及性能指标入手分析,在速度、精度、面积以及功耗折中的基础上确定了pipeline ADC整体架构,并辅以片上数字校正以纠正设计中带来的误差,以消除误差带来的性能影响,并降低功耗和面积。本论文基于SMIC 55nm工艺完成了10bit 200M流水线ADC的电路模块设计,数字校正,前仿和版图后仿。仿真结果显示:在电源电压1.2V,采样频率200MSPS,输入频率91MHz条件下,电路经过校正后的有效位数达到9.86bit,同时模拟电路功耗只有68mW。
[Abstract]:In modern electronic systems, almost all of them are digitized. In nature, signals are basically in the form of analogue, so an intermediate medium is needed to convert analog signals into digital signals. This medium is called analog-to-digital converter (ADC), which is widely used as a bridge between digital and analog, especially in the fields of digital signal processing, radar signal analysis, medical imaging equipment, multimedia equipment and so on. This thesis is based on the application background of high-definition digital video display. High speed, high precision and low power consumption are the embodiment of ADC advanced technology and the development trend in the future. High speed, high precision and low power ADC chips are designed with typical (flash), pipelined (pipeline), approximation structure (SAR) delta-sigma type. Because of the tradeoff in precision, speed, area and power consumption, pipeline ADC can be used in digital communication system, high-definition video display system and other fields. As the characteristic size of transistors in CMOS process is shortened and the performance of transistors, such as precision, speed, power consumption and so on, is continuously improved, the traditional design methods and structures can not meet the requirements. Therefore, digital correction technology emerged as the times require, which can greatly improve the performance of ADC. In this paper, the high speed, high precision and low power ADC is used as the research subject. Through the analysis of the structure and performance of pipeline ADC, the overall framework of pipeline ADC is determined on the basis of speed, precision, area and power compromise. It is supplemented by on-chip digital correction to correct the errors in the design so as to eliminate the performance effects caused by the errors and to reduce the power consumption and area. In this paper, the circuit module design, digital correction, precopy and post-layout simulation of 10bit 200M pipeline ADC are completed based on SMIC 55nm process. The simulation results show that under the conditions of power supply voltage 1.2 V, sampling frequency 200mSPS and input frequency 91MHz, the corrected effective bit number of the circuit is 9.86 bit, and the power consumption of the analog circuit is only 68 MW.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN792
本文编号：2236478
[Abstract]:In modern electronic systems, almost all of them are digitized. In nature, signals are basically in the form of analogue, so an intermediate medium is needed to convert analog signals into digital signals. This medium is called analog-to-digital converter (ADC), which is widely used as a bridge between digital and analog, especially in the fields of digital signal processing, radar signal analysis, medical imaging equipment, multimedia equipment and so on. This thesis is based on the application background of high-definition digital video display. High speed, high precision and low power consumption are the embodiment of ADC advanced technology and the development trend in the future. High speed, high precision and low power ADC chips are designed with typical (flash), pipelined (pipeline), approximation structure (SAR) delta-sigma type. Because of the tradeoff in precision, speed, area and power consumption, pipeline ADC can be used in digital communication system, high-definition video display system and other fields. As the characteristic size of transistors in CMOS process is shortened and the performance of transistors, such as precision, speed, power consumption and so on, is continuously improved, the traditional design methods and structures can not meet the requirements. Therefore, digital correction technology emerged as the times require, which can greatly improve the performance of ADC. In this paper, the high speed, high precision and low power ADC is used as the research subject. Through the analysis of the structure and performance of pipeline ADC, the overall framework of pipeline ADC is determined on the basis of speed, precision, area and power compromise. It is supplemented by on-chip digital correction to correct the errors in the design so as to eliminate the performance effects caused by the errors and to reduce the power consumption and area. In this paper, the circuit module design, digital correction, precopy and post-layout simulation of 10bit 200M pipeline ADC are completed based on SMIC 55nm process. The simulation results show that under the conditions of power supply voltage 1.2 V, sampling frequency 200mSPS and input frequency 91MHz, the corrected effective bit number of the circuit is 9.86 bit, and the power consumption of the analog circuit is only 68 MW.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN792
【参考文献】
相关期刊论文 前4条
1 郭英杰;王兴华;丁英涛;赵洪明;;一种12位100 MS/s流水线ADC的设计[J];微电子学;2016年06期
2 杨阳;张科峰;任志雄;刘览琦;;12 bit 200 MS/s时间交织流水线A/D转换器的设计[J];半导体技术;2015年09期
3 周佳;许丽丽;李福乐;王志华;;A 10-bit 120-MS/s pipelined ADC with improved switch and layout scaling strategy[J];Journal of Semiconductors;2015年08期
4 卢雪梅;刘士刚;石广源;;Pipeline ADC的噪声与采样电容的关系[J];辽宁大学学报(自然科学版);2009年01期
相关硕士学位论文 前1条
1 何红松;CMOS高性能运算放大器研究与设计[D];复旦大学;2009年
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