高速ADC中SPI接口电路的研究与设计

发布时间：2018-09-12 06:05

【摘要】：高速ADC在雷达、无线通信、高速数据采集等领域有着广泛的应用。作为完成对数据采样、转换工作的核心模块,ADC与外部控制器之间的数据传输,以及其性能的提升逐渐成为了芯片开发者们研究的热点。SPI接口总线因其具有传输速度快、占用信号线少、信号传输准确率高、全双工等优点,在数据通信中得到了广泛应用。因此,将SPI接口集成在高速ADC芯片中的设计理念已然成为了当前高速ADC开发的主流趋势。本文基于一款折叠插值架构的高速ADC,研究并设计了适用于高速ADC的SPI接口电路,实现了高速ADC与外部控制器的数据串行通信,并研究了对高速ADC的多功能配置,包括校准使能、数据时钟DCLK相位选择、多通道工作断电控制、编码测试功能等。通过采用SPI接口电路对ADC的配置方法,节约了芯片管脚数,可大大减小芯片面积。另外,还研究了通过SPI接口电路对高速ADC中失配误差进行校准,包括采样保持电路的失调失配以及时序产生电路的采样时间失配。这种手动校准的设计方法不但校准精度高,而且具有更好的灵活性和可控制性。本文利用Verlilog HDL硬件描述语言完成了 SPI接口电路的RTL级设计,利用Modelsim仿真软件对设计的SPI接口电路进行了功能仿真,验证了其功能的正确性,并在数模混合仿真平台CadenceAMS中,对RTL级的SPI接口电路和基于TSMC0.18μm CMOS工艺的误差校准电路进行级联仿真,结果表明通过SPI接口电路可以实现失配误差的校准,其中采样保持电路的ENOB从8.93bits提升至11.03bits,时序产生电路校准后的采样时序偏差为0.09ps,有效降低了电路的失配误差,提升了电路性能,从而改善高速ADC的整体性能。接着,对设计的SPI接口电路进行FPGA硬件实现与验证。最后,基于TSMC 0.18μm CMOS工艺库对SPI接口电路进行ASIC实现与验证,利用Design Compiler综合工具完成电路综合,得到综合后时序分析报告,结果表明该SPI接口电路时序满足设计要求,并对综合后的电路进行后仿真验证,然后利用IC Compiler工具实现了 SPI接口电路的自动布局布线,完成版图设计。
[Abstract]:High-speed ADC is widely used in radar, wireless communication, high-speed data acquisition and other fields. As the core module of data sampling and conversion, data transmission between ADC and external controllers, as well as the improvement of its performance, has gradually become a research hotspot for chip developers. With the advantages of fewer signal lines, high transmission accuracy and full duplex, SPI interface has been widely used in data communication. Therefore, the design concept of integrating SPI interface into high-speed ADC chip has become the mainstream trend of high-speed ADC development. SPI interface circuit realizes data serial communication between high-speed ADC and external controller, and studies the multi-functional configuration of high-speed ADC, including calibration enablement, data clock DCLK phase selection, multi-channel power-off control, coding and testing functions. In addition, the mismatch error in high-speed ADC is calibrated by SPI interface circuit, including mismatch of sampling and holding circuit and mismatch of sampling time in timing generation circuit. The RTL-level design of SPI interface circuit is completed with Verlilog HDL hardware description language. The function of the designed SPI interface circuit is simulated with Modelsim simulation software. The correctness of the function is verified. The RTL-level SPI interface circuit and the error calibration based on TSMC 0.18um CMOS process are implemented in CadenceAMS. The cascade simulation results show that the mismatch error can be calibrated by the SPI interface circuit. The ENOB of the sample and hold circuit is increased from 8.93 bits to 11.03 bits, and the sampling timing error is 0.09ps after the timing generation circuit is calibrated. The mismatch error of the circuit is effectively reduced and the performance of the circuit is improved. Finally, based on the TSMC 0.18um CMOS process library, the SPI interface circuit is implemented and verified by ASIC, and the circuit synthesis is completed by the Design Compiler synthesis tool. The timing analysis report is obtained after synthesis. The results show that the SPI interface circuit timing meets the design requirements. Then, the integrated circuit is simulated and verified, and the automatic layout and wiring of SPI interface circuit is realized by using IC Compiler.
【学位授予单位】：合肥工业大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN792

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