高线性低相噪压控振荡器电路设计

发布时间：2018-09-12 07:46

【摘要】：近年来,随着无线通讯技术的迅猛发展,CMOS射频集成电路和片上系统(SOC, System On Chip)的研究与应用已成为目前电子设计的主流技术。CMOS压控振荡器由于具有频率可控的优点,已成为无线通信系统中锁相环(PLL, Phase Locked Loop1电路的一个重要组成部分。而环形压控振荡器由于具有高线性、宽调谐、易集成、结构简单等优点而被广泛使用,其主要原因在于压控振荡器可以提供稳定的本振信号和电路所需的高频时钟信号,而电路的功耗、调节范围和相位噪声等指标均已成为近些年压控振荡器领域的研究热点内容。在国内外VCO(Voltage Control Oscillator)的研究现状的基础上,本文从振荡器的基本原理和实现方式出发,针对振荡器的系统理论模型和压控特性进行分析,分别阐述了LC振荡器和环形振荡器的基本架构。同时,本文主要针对振荡器电路的相位噪声特性进行建模分析和简要说明。在此基础上,重点分析了不同方式实现的压控单端延迟单元和差分延迟电路,并提出了一种具有高线性度、低相位噪声的压控振荡器电路方案。本文提出的压控振荡器电路采用TSMC 0.35μm CMOS工艺实现,基于Cadence平台实现电路的仿真验证,在Virtuoso下完成电路版图的绘制,并进行后仿真验证。其后仿真验证结果表明,在27℃下,振荡器输出频率的可调谐范围约为44MHz～163MHz(@1.0V～1.8V)。当频率约为104MHz时,在100kHz频偏处的相位噪声为-99.12dBc/Hz,在1MHz频偏处的相位噪声为-128.3dBc/Hz。
[Abstract]:In recent years, with the rapid development of wireless communication technology, the research and application of CMOS RF integrated circuit and SOC (System On Chip) have become the mainstream technology in electronic design. CMOS voltage controlled oscillator (VCO) has become one of the PLL (Phase Locked Loop 1) circuits in wireless communication systems because of its advantages of frequency controllability. The voltage controlled oscillator is widely used because of its high linearity, wide tuning, easy integration and simple structure. The main reason is that the voltage controlled oscillator can provide stable local oscillator signal and high frequency clock signal needed by the circuit. The power consumption, adjusting range and phase noise of the circuit have been achieved. Based on the research status of VCO (Voltage Control Oscillator) at home and abroad, this paper analyzes the theoretical model and voltage control characteristics of the oscillator, and expounds the basic theory of LC oscillator and ring oscillator respectively. At the same time, the phase noise characteristic of the oscillator circuit is modeled and analyzed briefly in this paper. On this basis, the voltage-controlled single-ended delay unit and differential delay circuit implemented in different ways are analyzed emphatically, and a voltage-controlled oscillator circuit scheme with high linearity and low phase noise is proposed. The VCO circuit is implemented by TSMC 0.35 micron CMOS technology. The circuit is simulated and verified based on Cadence platform. The circuit layout is plotted under Virtuoso and verified by post-simulation. The simulation results show that the tunable range of the output frequency of the VCO is about 44MHz to 163MHz (@1.0V to 1.8V) at 27 C. At about 104MHz, the phase noise at the frequency offset of 100 kHz is - 99.12 dBc/Hz and - 128.3 dBc/Hz at the frequency offset of 1 MHz.
【学位授予单位】：东南大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN752

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