光接收芯片内时钟数据恢复电路的设计

发布时间：2018-09-12 18:40

【摘要】：光纤通讯具有容量大、抗干扰能力强、传输距离远、节能等优点,成为目前研究的热门课题。在光纤通讯的过程中,需要时钟数据恢复电路提取时钟,并对数据进行重定时以抑制抖动。目前我国的主流光纤传输速率是2.5Gbps,随着光纤传输的速度和要求逐步提升,10Gbps的光纤传输速率必将成为未来的主流。因此本论文的主要目标是设计一款中心频率为10Gbps的时钟数据恢复(CDR)电路芯片。论文采用锁相环为基础的时钟数据恢复电路结构,电路包括鉴频器(FD)、鉴相器(PD)、低通滤波器(LPF)、电荷泵(CP)、压控振荡器(VCO)以及重定时模块。为减少抖动积累并产生高频振荡,采用低噪声结构的LC压控振荡器产生高频时钟信号。在电荷泵模块设立参考电平,保证控制电压的变化幅度限制在压控振荡器的线性区以内。鉴频器采用下降选频的新型结构以达到1.35GHz的超大范围频率捕捉,鉴相器采用前置D触发器优化过零点,并使时钟信号保持在数据位中间点采样,为抖动和不确定因素提供最大的裕度。鉴频器和鉴相器可在频率逼近后完成工作切换,缩短捕捉时间,提升了工作效率。通过调节环路参数使系统达到锁定。输入数据经过提取后的时钟重定时,输出抖动大大降低。在Cadence下对时钟数据恢复电路各个模块及整体进行了仿真分析,并给出了基于TSMC 0.18μm工艺的版图绘制和后仿真。前仿真结果表明,本文所设计的时钟数据恢复电路在3.3V的电源电压下整体功耗为90mW,恢复出的10GHz时钟相位噪声为-87.5dBc/Hz,压控振荡器压控增益为1.08GHz/V。在系统锁定后,输出时钟的峰峰值抖动为3ps,重定时后的数据输出抖动峰峰值为4.5ps。芯片版图面积为300μm×500μm,后仿真结果表明,系统锁定后输出时钟峰峰值抖动为6ps,重定时后的数据输出峰峰值抖动为10ps,对比输入数据15ps抖动,起到了很好的抖动抑制效果。
[Abstract]:Optical fiber communication has many advantages, such as large capacity, strong anti-interference ability, long transmission distance, energy saving and so on. In the process of optical fiber communication, the clock data recovery circuit is needed to extract the clock and retiming the data to suppress the jitter. At present, the main fiber transmission rate in China is 2.5Gbps.With the speed and requirement of fiber transmission, the fiber transmission rate of 10Gbps will become the mainstream in the future. Therefore, the main goal of this thesis is to design a clock data recovery (CDR) chip with center frequency of 10Gbps. In this paper, a clock data recovery circuit based on PLL is used. The circuit includes a frequency discriminator, a (FD), phase discriminator, a (PD), low-pass filter, a (LPF), charge pump (CP), voltage-controlled oscillator (VCO) and a retiming module. In order to reduce jitter accumulation and generate high frequency oscillation, a low noise LC voltage-controlled oscillator is used to generate high frequency clock signal. The reference level is set up in the charge pump module to ensure that the range of the control voltage is limited to the linear range of the VCO. The frequency discriminator adopts a new structure of descending frequency selection to achieve the 1.35GHz super wide frequency capture. The phase detector uses a preposition D flip-flop to optimize the zero crossing point and to keep the clock signal sampling at the middle of the data bit. Provides maximum margin for jitter and uncertainty. Frequency discriminator and phase discriminator can complete the switching after frequency approaching, shorten the capture time and improve the working efficiency. The system is locked by adjusting the loop parameters. After the input data is extracted, the output jitter is greatly reduced when the clock is retimed. Each module and whole of clock data recovery circuit are simulated and analyzed in Cadence, and the layout drawing and post simulation based on TSMC 0.18 渭 m technology are given. The pre-simulation results show that the overall power consumption of the designed clock data recovery circuit is 90 MW at 3.3 V supply voltage, the recovered 10GHz clock phase noise is -87.5 dBc / Hz, and the voltage control gain of the VCO is 1.08 GHz / V. After the system is locked, the peak jitter of the output clock is 3 pss, and the peak value of the data output jitter after retiming is 4.5 ps. The chip layout area is 300 渭 m 脳 500 渭 m. The post-simulation results show that the peak jitter of the output clock peak is 6 pss after locking and the peak jitter of the data output peak after retiming is 10 ps.Compared with the 15ps jitter of input data, the jitter suppression effect is very good.
【学位授予单位】：哈尔滨工业大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN929.11;TN402

【参考文献】