三维集成电路中硅通孔的建模与仿真研究
发布时间：2018-09-19 19:56
【摘要】：随着半导体器件特征尺寸不断接近材料物理极限,漏电流现象和热问题愈加突出,且随着互连线尺寸不断缩小,传统铜互连的延迟、噪声和功耗问题愈加严重,因而需要发展三维集成技术来延续甚至超越摩尔定律。作为三维集成电路的核心技术,硅通孔可实现信号在堆叠层器件间的电学连接,从而缩短互连长度,减小延迟和功耗,缩小芯片占用面积,实现高度集成及异质芯片集成。本论文针对硅通孔开展电路建模研究,发展准确、快速的电学参数提取技术,研究硅通孔信号传输性能及优化方法,相关工作可分为三部分:在第一部分中,研究碳纳米管作为硅通孔填充导体材料对电学性能的影响,给出碳纳米管填充硅通孔的等效电路模型,结合等效复电导率概念分析信号传输性能。考虑碳纳米管中动电感变化所带来的负面影响,证明将传统铜材料与碳纳米管混合构造新型导体材料,用于填充硅通孔以抑制碳纳米管动电感变化对高频性能稳定性的影响。第二部分致力于发展重布线层中水平互连线及差分硅通孔的宽带建模方法,给出能够在直流至100 GHz频率范围内适用的等效电路模型,并发展相应的参数提取技术。基于提出的等效电路模型,研究了设计参数及温度变化对电学性能的影响,相关成果对硅通孔的优化设计有所帮助。第三部分研究了浮硅基底中硅通孔的寄生电容建模方法,给出了典型三根硅通孔阵列的等效电路模型,结合非线性电容效应分析瞬态电压响应。同时还研究了内部为浮硅基底的同轴硅通孔,分析设计参数对非线性电容的影响。研究表明,浮硅基底下的硅通孔同样可通过在工艺中引入氧化层固定电荷,使硅通孔寄生电容在一定工作电压范围内稳定,从而简化建模和仿真过程。总之,本论文针对三维集成电路中硅通孔进行了一些探索,开展了电路建模和电学特性等方面的研究,得到了一些有益的结果。
[Abstract]:With the characteristic size of semiconductor devices approaching the material physical limit, leakage current phenomenon and thermal problems become more and more prominent, and the delay, noise and power consumption problems of traditional copper interconnection become more and more serious with the decreasing of interconnect size. Therefore, it is necessary to develop three-dimensional integration technology to extend or even exceed Moore's law. As the core technology of 3D integrated circuit, silicon through hole can realize the electrical connection between stacked devices, which can shorten the interconnect length, reduce the delay and power consumption, reduce the occupied area of the chip, and realize the high integration and the heterogeneous chip integration. In this paper, we develop circuit modeling research for silicon through hole, develop accurate and fast electrical parameter extraction technology, study the transmission performance and optimization method of silicon through hole signal. The related work can be divided into three parts: in the first part, The effect of carbon nanotubes (CNTs) on the electrical properties of silicon through porous conductors is studied. The equivalent circuit model of carbon nanotubes filled with silicon through holes is presented. The signal transmission performance is analyzed with the concept of equivalent complex conductivity. Considering the negative effect of dynamic inductance variation in carbon nanotubes, it is proved that a new type of conducting material is constructed by mixing traditional copper materials with carbon nanotubes to fill silicon through holes to suppress the influence of dynamic inductance variation on the stability of high frequency properties of carbon nanotubes. The second part is devoted to the development of broadband modeling method for horizontal interconnects and differential silicon through holes in rewiring layer. The equivalent circuit model which can be used in the frequency range from DC to 100 GHz is given and the corresponding parameter extraction technique is developed. Based on the proposed equivalent circuit model, the effects of design parameters and temperature changes on electrical properties are studied. In the third part, the parasitic capacitance modeling method of silicon through hole in floating silicon substrate is studied. The equivalent circuit model of three typical silicon through hole arrays is given, and the transient voltage response is analyzed with nonlinear capacitance effect. The influence of the design parameters on the nonlinear capacitance is analyzed. The results show that the silicon through hole under the floating silicon substrate can also be stabilized by introducing the fixed charge of the oxide layer in the process, so that the parasitic capacitance of the through hole can be stabilized in a certain working voltage range, thus simplifying the modeling and simulation process. In a word, this thesis has made some exploration on the silicon through hole in 3D integrated circuit, carried out circuit modeling and electrical characteristics, and got some useful results.
【学位授予单位】：杭州电子科技大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN40
本文编号：2251167
[Abstract]:With the characteristic size of semiconductor devices approaching the material physical limit, leakage current phenomenon and thermal problems become more and more prominent, and the delay, noise and power consumption problems of traditional copper interconnection become more and more serious with the decreasing of interconnect size. Therefore, it is necessary to develop three-dimensional integration technology to extend or even exceed Moore's law. As the core technology of 3D integrated circuit, silicon through hole can realize the electrical connection between stacked devices, which can shorten the interconnect length, reduce the delay and power consumption, reduce the occupied area of the chip, and realize the high integration and the heterogeneous chip integration. In this paper, we develop circuit modeling research for silicon through hole, develop accurate and fast electrical parameter extraction technology, study the transmission performance and optimization method of silicon through hole signal. The related work can be divided into three parts: in the first part, The effect of carbon nanotubes (CNTs) on the electrical properties of silicon through porous conductors is studied. The equivalent circuit model of carbon nanotubes filled with silicon through holes is presented. The signal transmission performance is analyzed with the concept of equivalent complex conductivity. Considering the negative effect of dynamic inductance variation in carbon nanotubes, it is proved that a new type of conducting material is constructed by mixing traditional copper materials with carbon nanotubes to fill silicon through holes to suppress the influence of dynamic inductance variation on the stability of high frequency properties of carbon nanotubes. The second part is devoted to the development of broadband modeling method for horizontal interconnects and differential silicon through holes in rewiring layer. The equivalent circuit model which can be used in the frequency range from DC to 100 GHz is given and the corresponding parameter extraction technique is developed. Based on the proposed equivalent circuit model, the effects of design parameters and temperature changes on electrical properties are studied. In the third part, the parasitic capacitance modeling method of silicon through hole in floating silicon substrate is studied. The equivalent circuit model of three typical silicon through hole arrays is given, and the transient voltage response is analyzed with nonlinear capacitance effect. The influence of the design parameters on the nonlinear capacitance is analyzed. The results show that the silicon through hole under the floating silicon substrate can also be stabilized by introducing the fixed charge of the oxide layer in the process, so that the parasitic capacitance of the through hole can be stabilized in a certain working voltage range, thus simplifying the modeling and simulation process. In a word, this thesis has made some exploration on the silicon through hole in 3D integrated circuit, carried out circuit modeling and electrical characteristics, and got some useful results.
【学位授予单位】：杭州电子科技大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN40
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相关期刊论文 前1条
1 王高峰;赵文生;;三维集成电路中的关键技术问题综述[J];杭州电子科技大学学报;2014年02期
相关博士学位论文 前1条
1 赵文生;三维集成电路中新型互连结构的建模方法与特性研究[D];浙江大学;2013年
，本文编号：2251167
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