针对封装半成品IC的条状并行测试研究

发布时间：2018-10-05 16:24

【摘要】：目前国内各种电子产品需求飞速增长,每年对集成电路芯片的需求量成几何增长,随着各类电子产品的数码化和大容量化,对芯片的需求还将大幅增长。这使得集成电路芯片的出货量大幅增长,也就需要厂商在相同的时间内提供更多的成品,从而对集成电路的设计、生产和测试提出了更高的要求。本文围绕集成电路测试环节,提出了以封装半成品集成电路为对象的条状并行测试的新方法,此方法以提高测试生产效率以及降低测试成本为目的。通过对条状测试的原理分析,总结条状测试对硬件设备的要求,以及测试软件环境设置的方式,生产环节中的疑难问题解决等,探讨出适合条状并行测试的方法和流程。并且把这种崭新的测试方法导入的测试量产当中,本次课题涉及的主要研究内容包括：1、封装半成品集成电路条状并行测试条件的研究制定：通过对整个条状并行测试过程的研究,特别是条状并行测试方式与传统单颗测试方式在生产效率上的分析比较,制定最适合条状并行测试的条件。2、封装半成品集成电路条状并行测试测试流程制定：通过对2种不同类型的封装类型,小外形集成电路封装(SOP)与方形扁平无引脚封装(QFN)制定出不同封装类型所需的条状测试的封装测试流程,创新性的提出了在小外形集成电路(SOP)封装类型中增加引脚分离制程(Trim)与方形扁平无引脚(QFN)封装类型中增加半切割制程(Half-cut)的新方法。3、封装半成品集成电路条状并行测试环境搭建和测试方法实施：结合实际生产环境,搭建相应的软硬件测试环境,并基于此提出条状并行测试的方式方法。4、封装半成品集成电路条状并行测试结果分析：提出测试结果判断方法、最终的成品筛选,识别方式等,针对每一制程,指定实验方法,确定可行性,形成完整方案并应用于实际生产中针对封装半成品集成电路的条状并行测试的新方法,突破了传统意义上的封装结束后再进行成品测试的模式,创新性的提出了半成品集成电路的测试模式,在封装的塑封制程完成之后,不是进行印字与切割而是进行引脚分离(Trim),进而可以实现产品在框架上进行电性测试。突破了传统成品测试必须进行单颗测试的模,实现了真正意义上的大规模测试,极大的提高了产品生产在规模化过程中的测试效率,可满足芯片短时间面市及大供货量的要求。
[Abstract]:At present, the demand for all kinds of electronic products in our country is increasing rapidly, and the demand for integrated circuit chips becomes geometric growth every year. With the digitalization and large capacity of all kinds of electronic products, the demand for chips will also increase substantially. As a result, the quantity of IC chips has increased greatly, which requires manufacturers to provide more finished products in the same time, thus putting forward higher requirements for IC design, production and testing. In this paper, a new method of strip parallel testing based on encapsulating semi-finished integrated circuits is proposed, which aims to improve the test production efficiency and reduce the test cost. Based on the analysis of the principle of strip testing, this paper summarizes the requirements of strip testing for hardware equipment, the way of setting up the test software environment, and the solution of difficult problems in production, and discusses the methods and flow chart suitable for strip parallel testing. And to import this new test method into the test production, The main research contents of this topic include: 1, the development of strip parallel test conditions for packaging semi-finished integrated circuits: through the research of the whole strip parallel testing process, In particular, the analysis and comparison of the production efficiency between the strip parallel test method and the traditional single test method, Develop the most suitable conditions for strip parallel testing. 2. Package the process of strip parallel testing for semi-finished integrated circuits: through two different types of packaging, The small shape integrated circuit package (SOP) and the square flat pin free package (QFN) develop the package test flow of the different packaging type required by the strip test. A new method of adding pin separation process (Trim) and square flat pin free (QFN) package type to (SOP) package type of small shape integrated circuit and adding half cut process (Half-cut) to the package type of square flat pin free (QFN) are proposed. 3, in order to package semi finished integrated circuit strip parallel, this paper proposes a new method of adding half cut process (Half-cut) to the package type of small shape integrated circuit. Test environment construction and test method implementation: combined with actual production environment, Build the corresponding software and hardware test environment, and based on this, put forward the method of strip parallel testing. 4, package the semi-finished integrated circuit strip parallel test results analysis: put forward the test result judgment method, the final product screening, the identification method and so on. For each process, the experimental method is specified, the feasibility is determined, the complete scheme is formed and applied to the new method of strip parallel testing for packaging semi-finished integrated circuits in actual production. Breaking through the traditional mode of testing finished product after packaging, innovatively putting forward the test mode of semi-finished IC, after the packaging process is finished, Instead of printing and cutting, a pin separation (Trim), can be used to test the electrical properties of the product on the frame. It breaks through the model that traditional finished product testing must carry out single test, realizes the real large-scale test, greatly improves the testing efficiency in the large-scale process of product production, and can meet the demand of short time market and large supply quantity of chip.
【学位授予单位】：上海交通大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN407

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