基于以太网接口的Turbo码编译码系统FPGA实现
发布时间：2018-10-12 08:20
【摘要】：Turbo码作为20世纪末通信行业最伟大的技术成就之一,它的提出在信道编码领域具有里程碑式的意义。它不仅拥有接近于Shannon限的性能,更为我们研究编码理论提供了新的思路和手段。Turbo码以其优越的性能得到了广泛的应用,自然也成为人们竞相研究的焦点。本文以Turbo码的研究为出发点,立足于Turbo码的硬件实现,并在Turbo码的研究基础上搭建了一个硬件通信平台,方便了对Turbo码硬件性能的分析。本文首先对Turbo码的基本理论进行了系统的研究,介绍了Turbo码编译码器的基本结构,推导了MAP类算法;同时进行了性能仿真,分析了影响Turbo码性能的因素。然后,利用滑窗算法的设计思路完成了Turbo码编译码器的FPGA实现。最后,为了能够灵活有效地对Turbo码的编译码器的硬件性能进行分析,提供了一种硬件系统解决方案。通过使用应用广泛的以太网技术搭建了编码器和译码器的联调系统。利用WinPcap技术,以以太网接口为桥梁实现了FPGA开发板和PC机之间的信息交换和处理,进而完成了整个基于以太网接口的Turbo码编译码系统的硬件实现。其间本文也对千兆以太网接口的FPGA实现进行了研究和设计。在系统测试上,给出了每一个数据处理过程的详细设计和仿真结果。为了完善整个系统,不仅考虑了收发包之间间隔时间的设置,而且在长帧的处理及其拆包、组包的设计上进行了相应的研究。最终完成了整个Turbo码硬件系统的设计和仿真,并分析和比较了硬件性能和浮点、定点量化处理性能之间的差别,达到了预期的设计要求。
[Abstract]:As one of the greatest technological achievements in the communication industry at the end of the 20th century, Turbo code has a landmark significance in the field of channel coding. It not only has the performance close to the Shannon limit, but also provides new ideas and means for us to study the coding theory. Turbo codes have been widely used for their superior performance, and naturally have become the focus of research. This paper takes the research of Turbo code as the starting point, based on the hardware realization of Turbo code, and builds a hardware communication platform based on the research of Turbo code, which facilitates the analysis of the hardware performance of Turbo code. In this paper, the basic theory of Turbo codes is systematically studied, the basic structure of Turbo codes and decoders is introduced, and the MAP class algorithm is deduced. At the same time, the performance simulation is carried out, and the factors influencing the performance of Turbo codes are analyzed. Then, the FPGA implementation of Turbo codec is accomplished by using the design idea of sliding window algorithm. Finally, in order to analyze the hardware performance of Turbo codec flexibly and effectively, a hardware system solution is provided. By using the widely used Ethernet technology, the combined modulation system of encoder and decoder is built. Using WinPcap technology, the information exchange and processing between FPGA development board and PC computer are realized by using Ethernet interface as bridge, and then the hardware implementation of the whole Turbo codec and decode system based on Ethernet interface is completed. Meanwhile, the FPGA implementation of Gigabit Ethernet interface is also studied and designed in this paper. In the system test, the detailed design and simulation results of each data processing process are given. In order to perfect the whole system, not only the setting of the interval between transceiver packets is considered, but also the design of long frame processing and packet unpacking is studied. Finally, the design and simulation of the whole hardware system of Turbo code are completed, and the differences among hardware performance, floating-point and fixed-point quantization processing performance are analyzed and compared, and the expected design requirements are achieved.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN911.22;TN791
本文编号：2265443
[Abstract]:As one of the greatest technological achievements in the communication industry at the end of the 20th century, Turbo code has a landmark significance in the field of channel coding. It not only has the performance close to the Shannon limit, but also provides new ideas and means for us to study the coding theory. Turbo codes have been widely used for their superior performance, and naturally have become the focus of research. This paper takes the research of Turbo code as the starting point, based on the hardware realization of Turbo code, and builds a hardware communication platform based on the research of Turbo code, which facilitates the analysis of the hardware performance of Turbo code. In this paper, the basic theory of Turbo codes is systematically studied, the basic structure of Turbo codes and decoders is introduced, and the MAP class algorithm is deduced. At the same time, the performance simulation is carried out, and the factors influencing the performance of Turbo codes are analyzed. Then, the FPGA implementation of Turbo codec is accomplished by using the design idea of sliding window algorithm. Finally, in order to analyze the hardware performance of Turbo codec flexibly and effectively, a hardware system solution is provided. By using the widely used Ethernet technology, the combined modulation system of encoder and decoder is built. Using WinPcap technology, the information exchange and processing between FPGA development board and PC computer are realized by using Ethernet interface as bridge, and then the hardware implementation of the whole Turbo codec and decode system based on Ethernet interface is completed. Meanwhile, the FPGA implementation of Gigabit Ethernet interface is also studied and designed in this paper. In the system test, the detailed design and simulation results of each data processing process are given. In order to perfect the whole system, not only the setting of the interval between transceiver packets is considered, but also the design of long frame processing and packet unpacking is studied. Finally, the design and simulation of the whole hardware system of Turbo code are completed, and the differences among hardware performance, floating-point and fixed-point quantization processing performance are analyzed and compared, and the expected design requirements are achieved.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN911.22;TN791
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