新型低阻通道三维横向MOS研究
发布时间：2018-10-13 09:09
【摘要】：横向功率MOSFET存在比导通电阻与击穿电压的折中关系,常见的改善方法有RESURF(Reduced surface field)技术和超结(Super Junction,SJ)技术,这两种技术皆通过增强耗尽来提高漂移区掺杂浓度。本文提出新的电流输运模式,构建多数载流子积累层,由积累层形成的低阻通道和中性漂移区共同传输电流,显著降低器件的导通电阻,打破了横向MOSFET的“硅极限”。本文提出两类新型的具有连续低阻通道的横向超结LDMOS。(1)具有槽型增强积累延伸栅(Enhanced-accumulation trench-type extending gate,TEG)的超结LDMOS(TEG SJ LDMOS),该结构的特征在于嵌入漂移区中的槽型增强积累延伸栅,TEG由高k介质及P柱区构成。槽型增强积累延伸栅有两个作用:一是正向导通时,在高k介质与N柱区界面形成多数载流子积累层,且高k介质增强电荷积累作用,多数载流子积累层联合沟道构成从源至漏的连续低阻通道,有效降低比导通电阻;二是高k介质辅助耗尽漂移区,调制器件体内电场。仿真表明,TEG SJ LDMOS耐压为197V,比导通电阻为1.09 mΩ?cm2。针对衬底辅助耗尽效应,提出两种柱区阶梯掺杂的TEG SJ LDMOS。一是N柱区阶梯掺杂TEG SJ LDMOS,阶梯掺杂的N柱区有效抑制衬底辅助耗尽效应且调制器件表面电场,耐压从197V提升至217V。二是P柱区阶梯掺杂TEG SJ LDMOS,P柱区在漏端采用轻掺杂P1区,P1区减少了衬底辅助耗尽引起的P型杂质过剩,保持超结区的电荷平衡,器件获得耐压218V。(2)具有辅助积累延伸栅(Assisted-accumulation extending gate,AEG)的SJ LDMOS。这类器件的主要特征是位于器件表面的辅助积累延伸栅,开态时,N柱区表面形成电子积累层,P柱区表面形成电子反型层,积累层与反型层联合沟道构成从源至漏的连续低阻通道,低阻通道显著降低器件比导通电阻。为改善SJ LDMOS的耐压,提出具有阶梯掺杂N型缓冲层的AEG SJ LDMOS(AEG-SNB SJ LDMOS)及具有P型埋层的AEG SJ LDMOS(AEG-PB SJ LDMOS)。阶梯掺杂N-buffer在源端和漏端提供非均匀的电荷补偿,有效抑制衬底辅助耗尽效应。通过仿真,AEG-SNB SJ LDMOS得到235V的耐压及2.92mΩ?cm2的比导通电阻。P型埋层减少源端过剩的补偿电荷,并调制器件表面电场。仿真表明,AEG-PB SJ LDMOS获得220V的耐压及3.05 mΩ?cm2的比导通电阻。
[Abstract]:Transverse power MOSFET has a trade-off between specific on-resistance and breakdown voltage. Common improvement methods include RESURF (Reduced surface field) technique and overjunction (Super Junction,SJ) technique, both of which increase the doping concentration in drift region by enhanced depletion. In this paper, a new current transport mode is proposed to construct the majority carrier accumulation layer. The low resistance channel and neutral drift region formed by the accumulation layer can significantly reduce the on-resistance of the device and break the "silicon limit" of the transverse MOSFET. In this paper, we present two new types of transversely superjunction LDMOS. (1) with grooved enhanced accumulative extension gate (Enhanced-accumulation trench-type extending gate,TEG) with continuous low resistance channels. The structure is characterized by embedded grooves in the drift region. TEG is composed of a slotted enhanced accumulative extended gate (TEG). High k medium and P column region. The groove-type enhanced accumulation extension gate has two functions: one is the formation of a majority carrier accumulation layer at the interface between the high k medium and the N column, and the enhancement of charge accumulation in the high k medium. The continuous low resistance channel from source to drain is formed by the combination of most carrier accumulative layer and channel, which can effectively reduce the specific on-resistance; second, the high k dielectric auxiliary depletion drift region and the internal electric field of the modulator. The simulation results show that the, TEG SJ LDMOS voltage is 197V and the specific on-resistance is 1.09 m 惟? cm2.. In this paper, two kinds of pillared step doped TEG SJ LDMOS. are proposed for substrate assisted depletion effect. The first is that the N-column region doped with TEG SJ LDMOS, step in the N column region can effectively suppress the substrate assisted depletion effect and the electric field on the surface of the modulator, and the withstand voltage is raised from 197V to 217V. On the other hand, the step doped TEG SJ LDMOS,P column in P column region adopts light doping P1 region at the leakage end, which reduces the excess P-type impurity caused by substrate assisted depletion and keeps the charge balance in the superjunction region. (2) SJ LDMOS. with auxiliary accumulative extension gate (Assisted-accumulation extending gate,AEG). The main characteristic of this kind of devices is that the auxiliary accumulative extension gate is located on the surface of the device. In the open state, the electron accumulation layer is formed on the N column surface and the electron inversion layer is formed on the P column surface. The accumulation layer and the inversion layer combine the channel to form the continuous low resistance channel from the source to the drain, and the low resistance channel reduces the specific on-resistance of the device significantly. In order to improve the voltage resistance of SJ LDMOS, AEG SJ LDMOS (AEG-SNB SJ LDMOS) with step doped N-type buffer layer and AEG SJ LDMOS (AEG-PB SJ LDMOS). With P-type buried layer were proposed. Step doped N-buffer provides nonuniform charge compensation at the source and drain ends, which effectively inhibits the substrate-assisted depletion effect. The simulation results show that the voltage of 235V and the specific on-resistance of 2.92m 惟? cm2 are obtained by AEG-SNB SJ LDMOS. The P-type burying layer reduces the excess compensation charge at the source end and modulates the surface electric field of the device. The simulation results show that the AEG-PB SJ LDMOS has a voltage of 220 V and a specific on-resistance of 3.05 m 惟? cm2.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN386
本文编号：2268048
[Abstract]:Transverse power MOSFET has a trade-off between specific on-resistance and breakdown voltage. Common improvement methods include RESURF (Reduced surface field) technique and overjunction (Super Junction,SJ) technique, both of which increase the doping concentration in drift region by enhanced depletion. In this paper, a new current transport mode is proposed to construct the majority carrier accumulation layer. The low resistance channel and neutral drift region formed by the accumulation layer can significantly reduce the on-resistance of the device and break the "silicon limit" of the transverse MOSFET. In this paper, we present two new types of transversely superjunction LDMOS. (1) with grooved enhanced accumulative extension gate (Enhanced-accumulation trench-type extending gate,TEG) with continuous low resistance channels. The structure is characterized by embedded grooves in the drift region. TEG is composed of a slotted enhanced accumulative extended gate (TEG). High k medium and P column region. The groove-type enhanced accumulation extension gate has two functions: one is the formation of a majority carrier accumulation layer at the interface between the high k medium and the N column, and the enhancement of charge accumulation in the high k medium. The continuous low resistance channel from source to drain is formed by the combination of most carrier accumulative layer and channel, which can effectively reduce the specific on-resistance; second, the high k dielectric auxiliary depletion drift region and the internal electric field of the modulator. The simulation results show that the, TEG SJ LDMOS voltage is 197V and the specific on-resistance is 1.09 m 惟? cm2.. In this paper, two kinds of pillared step doped TEG SJ LDMOS. are proposed for substrate assisted depletion effect. The first is that the N-column region doped with TEG SJ LDMOS, step in the N column region can effectively suppress the substrate assisted depletion effect and the electric field on the surface of the modulator, and the withstand voltage is raised from 197V to 217V. On the other hand, the step doped TEG SJ LDMOS,P column in P column region adopts light doping P1 region at the leakage end, which reduces the excess P-type impurity caused by substrate assisted depletion and keeps the charge balance in the superjunction region. (2) SJ LDMOS. with auxiliary accumulative extension gate (Assisted-accumulation extending gate,AEG). The main characteristic of this kind of devices is that the auxiliary accumulative extension gate is located on the surface of the device. In the open state, the electron accumulation layer is formed on the N column surface and the electron inversion layer is formed on the P column surface. The accumulation layer and the inversion layer combine the channel to form the continuous low resistance channel from the source to the drain, and the low resistance channel reduces the specific on-resistance of the device significantly. In order to improve the voltage resistance of SJ LDMOS, AEG SJ LDMOS (AEG-SNB SJ LDMOS) with step doped N-type buffer layer and AEG SJ LDMOS (AEG-PB SJ LDMOS). With P-type buried layer were proposed. Step doped N-buffer provides nonuniform charge compensation at the source and drain ends, which effectively inhibits the substrate-assisted depletion effect. The simulation results show that the voltage of 235V and the specific on-resistance of 2.92m 惟? cm2 are obtained by AEG-SNB SJ LDMOS. The P-type burying layer reduces the excess compensation charge at the source end and modulates the surface electric field of the device. The simulation results show that the AEG-PB SJ LDMOS has a voltage of 220 V and a specific on-resistance of 3.05 m 惟? cm2.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN386
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1 田瑞超;新型低阻通道三维横向MOS研究[D];电子科技大学;2015年
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