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高速低功耗触发器的设计与特性提取

发布时间:2018-10-16 19:37
【摘要】:在超大规模集成电路设计中选择合适的触发器结构是非常重要的,尤其是在高速、低功耗微处理器的设计中显得尤为突出。触发器的延时在整个时钟周期中占据着重要位置,并且在深亚微米工艺中逻辑长度也更短的情况下,触发器的性能对处理器的时钟频率有着重要的影响。触发器和其他单元共同作用于时钟的产生和传播,其功耗占据全芯片功耗的20%-40%。所以研究高性能低功耗触发器对于超大规模集成电路有着重要的作用。本课题主要针对高性能低功耗触发器做了详细的研究和仿真,主要研究了以下几个方面的内容。1)高性能低功耗D触发器的设计与仿真本文中设计的触发器有两种,第一种是自适应耦合触发器(adaptive-coupling flip-flop,ACFF),该触发器的特点是功耗比较低,相对于传统主从型触发器功耗减少了8.43%,相对于脉冲型触发器减少了55.28%;第二种是脉冲型触发器(Transmisson Gate Plulsed Latch,TGPL),其优势是速度快。在后面电路和版图级的仿真中得出的数据可以看到TGPL的性能相对于主从型触发器提升45%左右。在后端物理设计中所查看的时序都是参考各个标准单元以及宏模块的特性视图(LIB视图),在完成触发器的设计与仿真之后对所设计的触发器进行了特性视图的抽取,并且对不同方法进行了实验和比较。2)D触发器测试电路的设计与仿真为了证明所设计的D触发器能正常工作,并且提取的时序特征是可靠的,在本文中设计了对触发器进行实测的测试电路,测试电路主要分为三部分,第一部分是延时(时钟到输出的延时)测量模块;第二部分是功耗测量模块;第三部分是建立保持时间测量模块(TDC)。在电路级仿真中,延时测量模块测量误差为7%左右(5ps以内),建立保持时间测量模块的精度可以达到1.25ps,功耗部分的测量也兼顾了不同翻转率的情况,对不同的设计进行了全面的对比。综上所述,本课题包括高性能低功耗D触发器的设计、特性提取以及实测模块,对触发器进行全面的分析和测量,在获得时序上的提升以及能量利用率提高的同时,也保证了触发器的可靠性。
[Abstract]:It is very important to choose the appropriate trigger structure in the design of VLSI, especially in the design of high speed and low power microprocessor. The delay of flip-flop occupies an important position in the whole clock cycle, and the performance of flip-flop has an important influence on the clock frequency of the processor when the logic length is shorter in the deep sub-micron process. Flip-flop and other units work together to generate and propagate the clock, and its power consumption accounts for 20-40% of the whole chip power. Therefore, the research of high performance and low power flip-flop plays an important role in VLSI. This paper mainly focuses on the research and simulation of high performance and low power flip-flop. It mainly studies the following aspects. 1) the design and simulation of high performance low power D flip-flop have two kinds of flip-flop designed in this paper. The first is adaptive coupled flip-flop (adaptive-coupling flip-flop,ACFF), which is characterized by low power consumption. Compared with the traditional master-slave flip-flop, the power consumption is reduced by 8.43 steps, compared with the pulse flip-flop, the power consumption is reduced by 55.28%, and the second type is the pulse-type flip-flop (Transmisson Gate Plulsed Latch,TGPL), which has the advantage of fast speed. The data obtained from the simulation of circuit and layout level show that the performance of TGPL is about 45% higher than that of master-slave flip-flop. In order to prove that the designed D flip-flop works normally, and the extracted timing features are reliable, the experiment and comparison of different methods are carried out. 2) the design and simulation of the D flip-flop test circuit are carried out in order to prove that the designed D-flip-flop works normally. The third part is the establishment of the retention time measurement module (TDC). In the circuit level simulation, the measurement error of the delay measurement module is about 7% (within 5ps), the accuracy of the building and holding time measurement module can reach 1.25 pss. the measurement of the power consumption part also takes into account the situation of different turnover rate. A comprehensive comparison of the different designs is made. To sum up, this topic includes the design of high performance and low power D flip-flop, the characteristic extraction and the actual measurement module, and the comprehensive analysis and measurement of the flip-flop, which can improve the timing and energy utilization at the same time. It also ensures the reliability of trigger.
【学位授予单位】:国防科学技术大学
【学位级别】:硕士
【学位授予年份】:2015
【分类号】:TN783

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