基于NoC的容错和低功耗编解码设计

发布时间：2018-10-20 17:08

【摘要】：三维片上网络(3D Network on Chip,3D NoC)层间采用硅通孔(Through Silicon Vias, TSV)互联。受限于制造工艺,芯片成品率随互联TSV数目的增加急剧降低,这不仅影响芯片通讯可靠性,甚至对3D NoC技术适用度提出严峻考验。此外,芯片复杂度提高使得功耗问题日益凸显,过大的功耗导致芯片温度急剧升高,严重影响芯片可靠性和性能,增加芯片面积和封装成本。针对成品率问题,本文提出一种容错机制,当链路中部分TSV故障时,确保通讯正常。针对功耗问题,本文设计两种低功耗编解码电路来降低NoC功耗。本文主要工作如下：1.提出自适应位宽重组机制根据故障通道中功能正常的TSV数目,实现传输数据位宽的自适应重组,重组后的数据位宽与功能正常TSV数目一致,从而利用所有功能正常的TSV进行层间通讯。其核心电路设计为可以单周期完成数据移位和加载且移位位宽可变的移位寄存器,用以降低数据位宽重组时的操作周期,提高位宽重组效率。本文所设计电路提高了芯片成品率,降低了由于引入容错电路带来的传输延迟,其最大可以容忍(N-1/N)%的TSV故障率(N为TSV总数),相对已有容错方法,传输延迟最大可以降低49%。2.设计实现两种低功耗编解码电路针对互连线自翻转,采用翻转编码算法,引入分组编码思想,将数据分成4组分别应用编码算法,达到一个较好的降低功耗效果。结合本项目中NoC所定义的数据包格式同时考虑到翻转编码算法对于连续数据表现较差的缺点,引入格雷码组成联合编码。针对相邻互连线间的耦合翻转,采用E/O BI编码算法,细分编码算法步骤,同时引入选通时钟,同一时刻只有一个模块工作,从而有效降低功耗。实验结果表明,翻转编码降低了12.1%的NoC功耗,E/O BI编码降低了13.7%的NoC功耗。
[Abstract]:Three-dimensional on-chip network (3 D Network on Chip,3D NoC) layers are interlinked by silicon through hole (Through Silicon Vias, TSV). Limited by the manufacturing process, the chip yield decreases sharply with the increase of the number of interconnected TSV, which not only affects the reliability of chip communication, but also puts forward a severe test to the applicability of 3D NoC technology. In addition, the increase of chip complexity makes the problem of power consumption increasingly prominent. Excessive power consumption leads to a sharp rise in chip temperature, which seriously affects the reliability and performance of the chip, and increases the chip area and packaging cost. In this paper, we propose a fault-tolerant mechanism to ensure the normal communication when some TSV faults occur in the link. Aiming at the problem of power consumption, this paper designs two low-power codec circuits to reduce NoC power consumption. The main work of this paper is as follows: 1. An adaptive bit width recombination mechanism is proposed to realize the adaptive recombination of the transmission bit width according to the number of TSV with normal function in the fault channel. The reconstructed data bit width is consistent with the normal number of TSV. Thus, all the normal functions of the TSV for interlayer communication. Its core circuit is designed as a shift register which can complete data shift and load in a single period and the shift bit width is variable to reduce the operation period of data bit width recombination and improve the efficiency of bit width recombination. The circuit designed in this paper improves the chip yield and reduces the transmission delay caused by the introduction of fault-tolerant circuits. The maximum TSV failure rate of (N-1N)% (N is the total number of TSV) can be tolerated. Compared with the existing fault-tolerant methods, the maximum transmission delay can be reduced by 49.2. The design and implementation of two low-power codec circuits for interconnection self-flipping, using the flipping coding algorithm, introducing the idea of block coding, the data are divided into four groups to apply the coding algorithm, to achieve a better power consumption reduction effect. Combined with the packet format defined by NoC in this project and taking into account the disadvantage of flipping coding algorithm for continuous data performance, the joint coding is composed of Graycode. In view of the coupling and flipping between adjacent interconnects, the E / O BI coding algorithm, the step of subdivision coding algorithm and the introduction of strobe clock are used to work with only one module at the same time, thus effectively reducing the power consumption. The experimental results show that the flip coding reduces NoC power consumption by 12.1%, and the E / O BI code reduces the NoC power consumption by 13.7%.
【学位授予单位】：合肥工业大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TN47

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