基于纳米工艺的高速自适应均衡技术的研究与实现
发布时间：2018-10-21 19:23
【摘要】：当今无线通信系统、光纤通信系统和背板传输系统等各类通信系统为人们提供了高质量、高便捷的信息服务,极大促进了人们的生活和社会的发展。随着通信技术的高速发展,由于信道的衰减、串扰以及反射等非理想因素,高速信号在传输过程中会发生失真的现象也越来越严重。均衡正是通过对信道传输特性进行补偿来处理码间串扰(ISI)的一种技术,其目的是提高信号完整性,降低系统误码率。然而,随着信号速率的增加,高速均衡器尤其是自适应高速均衡器的设计与实现面临着严峻的挑战,需要在电路工作速度、补偿能力、自适应性以及面积和功耗等方面进行优化,并实现它们之间的良好折中,以满足通信系统日益增长的技术要求。本文对高速串行通信中的自适应均衡器的结构进行了研究,并在均衡结构优化的基础上,采用CMOS工艺设计了多个应用于接收端的高速均衡器并进行了流片和验证。本文首先从频域和时域的角度分析了高速背板信道的的损耗、串扰、反射及噪声等非理想特性对信号传输的影响。据此结合已有的主流均衡技术及其适应条件,基于ADS仿真平台对典型的背板信道进行了仿真,通过分析比较,综合考虑面积、功耗和可行性等因素,选取优化的线性均衡器(LE)和判决反馈均衡器(DFE)组合方案,为后续均衡器结构与电路的研究设计打下了基础。根据仿真得到的组合均衡器结构,本文设计了用于接收端的高速前馈均衡器(FFE)+DFE组合均衡器。通过分析比较波特间隔均衡器(BSE)和分数间隔均衡器(FSE)的特性,选取FSE结构来减小频谱混叠和采样偏差的影响。针对传统的DFE结构很难满足高速DFE设计要求的问题,本文采用半速率结构以提高信号的传输速率和时钟信号的准确性。此外,在FFE电路的设计过程中,采用有源并联电感峰化技术来增加延迟线带宽。在此基础上,本文基于TSMC 0.18μm CMOS工艺设计实现了FFE+DFE的高速均衡器,并进行了流片和测试。测试结果显示其在6.25Gb/s的传输速率下均衡输出眼图的水平张开度达到0.84UI,可以很好地补偿信道在6.25GHz处达22dB的衰减。在成功设计了高速FFE+DFE组合均衡器的基础上,本文进一步研究并设计了一个10Gb/s连续时间线性均衡器(CTLE)+DFE组合均衡器,解决了由于FFE的带宽受工艺截止频率的限制以及延迟电路对工艺偏差敏感所导致的组合均衡器工作速度受限的问题。通过分析比较无源RLC滤波器和有源差分滤波器两种结构的特点,设计了基于有源差分滤波器的CTLE,并在电路中引入了调谐功能,使CTLE能够有效地对信道进行补偿。本文基于TSMC 0.18μmmCMOS工艺设计实现的CTLE+DFE组合均衡器已成功流片并进行了测试,测试结果显示在10Gb/s的传输速率下均衡输出眼图的水平张开度达到0.63UI,对在10GHz处衰减达3 1dB的信道有很好的均衡作用。在对组合均衡器的结构和电路以及其自适应实现方式充分研究的基础上,本文采用IBM 0.13μmBiCMOS工艺设计实现了20Gb/s+的CTLE+DFE的自适应均衡器。其中,CTLE采用基于斜率比较的自适应结构,并对电路进行了优化,减小了电路的面积和功耗。DFE中抽头系数的更新则采用模拟LMS算法电路,实现了速度和性能的良好折中。同时,为了满足20Gb/s及以上信号速率的时序要求,DFE的主体结构采用半速率预处理结构以降低反馈路径的延迟时间。本文的最后给出了所设计的自适应均衡器的芯片照片和测试结果,整个芯片包括焊盘在内的芯片面积为0.78×O.8mm2。测试结果表明当速率为20Gb/s的信号经过20GHz处的衰减达20dB,反射达13dB的背板信道时,信道末端的眼图早已完全闭合,经过自适应均衡器后,输出眼图的水平张开度达到了0.85UI。该均衡器最高可工作在24Gb/s的速率上,对应的输出眼图张开度为0.81UI。在3.3V的电源电压下,功耗为624mW。目前国内在高速均衡器设计与实现方面与国际上仍有一定差距,本文的工作不仅能够推动相关领域的研究进一步向前发展,具有重要的学术价值,而且对我国高速集成电路的设计也具有重要的应用价值。
[Abstract]:Nowadays, various communication systems, such as wireless communication system, optical fiber communication system and backplane transmission system, provide high-quality and convenient information service for people, which greatly promotes the development of people's life and society. With the rapid development of communication technology, the distortion of high-speed signal in transmission process is becoming more and more serious due to non-ideal factors such as fading, crosstalk and reflection. equalization is a technique to deal with inter-code crosstalk (isi) by compensating channel transmission characteristics with the aim of improving signal integrity and reducing system error rate. However, as the signal rate increases, the design and implementation of high-speed equalizer, especially adaptive high-speed equalizer, faces severe challenges, and needs to be optimized in terms of circuit operating speed, compensation capacity, self-adaptability and area and power consumption, etc. and to achieve a good compromise between them to meet the increasing technical requirements of the communication system. In this paper, the structure of adaptive equalizer in high-speed serial communication is studied. Based on the optimization of the equalization structure, a plurality of high-speed equalizer applied to the receiving end is designed by CMOS process and the flow slice and verification are carried out. Firstly, the effects of non-ideal characteristics such as loss, crosstalk, reflection and noise on signal transmission are analyzed from the frequency domain and time domain. according to the existing mainstream equalization technology and the adaptation conditions, the typical backplane channel is simulated based on the ADS simulation platform, and the factors such as area, power consumption and feasibility are comprehensively considered through analysis and comparison, A combination of optimized linear equalizer (LE) and decision feedback equalizer (DFE) is chosen, which lays a foundation for the research and design of the following equalizer structure and circuit. In this paper, a high-speed feedforward equalizer (FFE) + DFE combined equalizer is designed for the receiving end according to the combined equalizer structure obtained by simulation. By analyzing the characteristics of the BSE and FSE, the FSE structure is selected to reduce the influence of frequency spectrum aliasing and sampling deviation. Aiming at the problem that the traditional DFE structure is difficult to meet the requirement of high-speed DFE design, the half-rate structure is adopted to improve the transmission rate of the signal and the accuracy of the clock signal. In addition, in the design process of FFE circuit, active parallel inductive peaking technology is used to increase the delay line bandwidth. On the basis of this, the high-speed equalizer of FFE + DFE is designed and implemented on the basis of TSMC 0. 18um CMOS process design, and the flow slice and test are carried out. The test results show that the horizontal opening degree of the equalized output signal at the transmission rate of 6,25Gb/ s reaches 0. 84UI, and the attenuation of 22dB at 6.25GHz can be well compensated. Based on the successful design of high speed FFE + DFE combined equalizer, a 10Gb/ s continuous time linear equalizer (CTLE) + DFE combined equalizer is further studied and designed. and solves the problem of limited working speed of the combined equalizer caused by the limitation of the cut-off frequency of the FFE and the sensitivity of the delay circuit to the process deviation. In this paper, the CTLE based on the active differential filter is designed and the tuning function is introduced in the circuit by analyzing the characteristics of the two structures of the non-source RLC filter and the active differential filter, so that the CTLE can effectively compensate the channel. The CTLE + DFE combined equalizer based on TSMC 0. 18. m CMOS process design has been successfully streamed and tested. The results show that the horizontal opening degree of the balanced output bridge at 10Gb/ s is 0.63UI, which has a good equalization effect on the channel with attenuation up to 31dB at 10GHz. Based on the full research on the structure and circuit of the combined equalizer and its adaptive implementation, the adaptive equalizer of 20Gb/ s + CTLE + DFE is designed in this paper. CTLE adopts self-adapting structure based on slope comparison, optimizes the circuit, reduces the area and power consumption of the circuit. The updating of tap coefficients in DFE uses an analog LMS algorithm circuit to achieve a good compromise between speed and performance. Meanwhile, in order to meet the timing requirement of 20Gb/ s and above signal rate, the main structure of DFE adopts half rate preprocessing structure to reduce the delay time of the feedback path. In the end of this paper, the chip photo and test result of the adaptive equalizer are presented. The chip area of the whole chip including the welding disc is 0.078 mmO. 8mm2. The test results show that when the signal rate of 20Gb/ s reaches 20dB at 20GHz and 13dB back plate channel is reflected, the horizontal opening of the end of the channel has been completely closed. After the adaptive equalizer, the horizontal opening degree of the output terminal reaches 0. 85UI. The equalizer can operate at a rate of 24Gb/ s, and the corresponding output value is 0. 81UI. At a power supply voltage of 3.3V, the power consumption is 624mW. At present, there are still some gaps in the design and implementation of high-speed equalizer in China. The work of this paper not only can promote further development of research in relevant fields, but also has important academic value, and also has important application value to the design of high-speed integrated circuit in China.
【学位授予单位】：东南大学
【学位级别】：博士
【学位授予年份】：2015
【分类号】：TN715
本文编号：2286114
[Abstract]:Nowadays, various communication systems, such as wireless communication system, optical fiber communication system and backplane transmission system, provide high-quality and convenient information service for people, which greatly promotes the development of people's life and society. With the rapid development of communication technology, the distortion of high-speed signal in transmission process is becoming more and more serious due to non-ideal factors such as fading, crosstalk and reflection. equalization is a technique to deal with inter-code crosstalk (isi) by compensating channel transmission characteristics with the aim of improving signal integrity and reducing system error rate. However, as the signal rate increases, the design and implementation of high-speed equalizer, especially adaptive high-speed equalizer, faces severe challenges, and needs to be optimized in terms of circuit operating speed, compensation capacity, self-adaptability and area and power consumption, etc. and to achieve a good compromise between them to meet the increasing technical requirements of the communication system. In this paper, the structure of adaptive equalizer in high-speed serial communication is studied. Based on the optimization of the equalization structure, a plurality of high-speed equalizer applied to the receiving end is designed by CMOS process and the flow slice and verification are carried out. Firstly, the effects of non-ideal characteristics such as loss, crosstalk, reflection and noise on signal transmission are analyzed from the frequency domain and time domain. according to the existing mainstream equalization technology and the adaptation conditions, the typical backplane channel is simulated based on the ADS simulation platform, and the factors such as area, power consumption and feasibility are comprehensively considered through analysis and comparison, A combination of optimized linear equalizer (LE) and decision feedback equalizer (DFE) is chosen, which lays a foundation for the research and design of the following equalizer structure and circuit. In this paper, a high-speed feedforward equalizer (FFE) + DFE combined equalizer is designed for the receiving end according to the combined equalizer structure obtained by simulation. By analyzing the characteristics of the BSE and FSE, the FSE structure is selected to reduce the influence of frequency spectrum aliasing and sampling deviation. Aiming at the problem that the traditional DFE structure is difficult to meet the requirement of high-speed DFE design, the half-rate structure is adopted to improve the transmission rate of the signal and the accuracy of the clock signal. In addition, in the design process of FFE circuit, active parallel inductive peaking technology is used to increase the delay line bandwidth. On the basis of this, the high-speed equalizer of FFE + DFE is designed and implemented on the basis of TSMC 0. 18um CMOS process design, and the flow slice and test are carried out. The test results show that the horizontal opening degree of the equalized output signal at the transmission rate of 6,25Gb/ s reaches 0. 84UI, and the attenuation of 22dB at 6.25GHz can be well compensated. Based on the successful design of high speed FFE + DFE combined equalizer, a 10Gb/ s continuous time linear equalizer (CTLE) + DFE combined equalizer is further studied and designed. and solves the problem of limited working speed of the combined equalizer caused by the limitation of the cut-off frequency of the FFE and the sensitivity of the delay circuit to the process deviation. In this paper, the CTLE based on the active differential filter is designed and the tuning function is introduced in the circuit by analyzing the characteristics of the two structures of the non-source RLC filter and the active differential filter, so that the CTLE can effectively compensate the channel. The CTLE + DFE combined equalizer based on TSMC 0. 18. m CMOS process design has been successfully streamed and tested. The results show that the horizontal opening degree of the balanced output bridge at 10Gb/ s is 0.63UI, which has a good equalization effect on the channel with attenuation up to 31dB at 10GHz. Based on the full research on the structure and circuit of the combined equalizer and its adaptive implementation, the adaptive equalizer of 20Gb/ s + CTLE + DFE is designed in this paper. CTLE adopts self-adapting structure based on slope comparison, optimizes the circuit, reduces the area and power consumption of the circuit. The updating of tap coefficients in DFE uses an analog LMS algorithm circuit to achieve a good compromise between speed and performance. Meanwhile, in order to meet the timing requirement of 20Gb/ s and above signal rate, the main structure of DFE adopts half rate preprocessing structure to reduce the delay time of the feedback path. In the end of this paper, the chip photo and test result of the adaptive equalizer are presented. The chip area of the whole chip including the welding disc is 0.078 mmO. 8mm2. The test results show that when the signal rate of 20Gb/ s reaches 20dB at 20GHz and 13dB back plate channel is reflected, the horizontal opening of the end of the channel has been completely closed. After the adaptive equalizer, the horizontal opening degree of the output terminal reaches 0. 85UI. The equalizer can operate at a rate of 24Gb/ s, and the corresponding output value is 0. 81UI. At a power supply voltage of 3.3V, the power consumption is 624mW. At present, there are still some gaps in the design and implementation of high-speed equalizer in China. The work of this paper not only can promote further development of research in relevant fields, but also has important academic value, and also has important application value to the design of high-speed integrated circuit in China.
【学位授予单位】：东南大学
【学位级别】：博士
【学位授予年份】：2015
【分类号】：TN715
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