一种低失调高PSRR的带隙基准电路
发布时间：2018-10-26 08:40
【摘要】：针对带隙基准的精度会影响集成电路的性能问题,提出了一种新的带隙基准电路结构.通过采用负反馈补偿网络来增强电源抑制比,降低失调电压,从而提高了电路的稳定性和精度.基于SMIC 0.18μm 1.8V CMOS工艺,利用Cadence spectre仿真,结果表明:在-30℃~100℃温度范围内,温漂系数为34.6×10~(-6)/℃;低频下电源抑制比为-63.5dB;功耗仅1.5μW.该电路适用于低压低功耗能量获取系统.
[Abstract]:Aiming at the problem that the precision of bandgap reference affects the performance of integrated circuit, a new band-gap reference circuit structure is proposed. The negative feedback compensation network is used to enhance the power supply rejection ratio and reduce the offset voltage, thus improving the stability and accuracy of the circuit. Based on SMIC 0.18 渭 m 1.8V CMOS process and Cadence spectre simulation, the results show that the temperature drift coefficient is 34.6 脳 10 ~ (-6) / 鈩，
本文编号：2295172
[Abstract]:Aiming at the problem that the precision of bandgap reference affects the performance of integrated circuit, a new band-gap reference circuit structure is proposed. The negative feedback compensation network is used to enhance the power supply rejection ratio and reduce the offset voltage, thus improving the stability and accuracy of the circuit. Based on SMIC 0.18 渭 m 1.8V CMOS process and Cadence spectre simulation, the results show that the temperature drift coefficient is 34.6 脳 10 ~ (-6) / 鈩，
本文编号：2295172
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