5V工艺下SCR结构在ESD应力下的特性研究及优化
发布时间：2018-10-26 10:52
【摘要】：随着集成电路制造工艺的发展,芯片的尺寸越来越小,在带来芯片速度以及性能方面快速提升的同时,其更容易被静电释放(ElectroStatic discharge,简称ESD)脉冲损毁。目前,半导体工业界大约有高达30%的芯片失效是由ESD造成,每年由ESD所造成的损失高达数十亿美元。ESD可能对芯片造成两种问题,一种是直接损毁导致芯片功能丧失,这种损毁在生产时能够被检测出来。二是对芯片内部电路产生非致命性损毁,这种损毁在生产时无法检测,而随着用户使用时间的增加,芯片性能变得不稳定,引起寿命降低,影响公司信誉。因此,设计出合格的ESD保护结构是提高成品率,树立公司信誉的关键。本文则针对5 V工艺下的IC进行ESD保护研究,并重点研究SCR(Silicon Controlled Rectifier,可控硅整流器)用于5V IC的ESD保护时所存在的问题并优化SCR结构。本文先简单介绍ESD防护理论与常用的ESD保护器件,如:二极管,BJT,GGNMOS,SCR。通过TLP(Transmission Line Pulse,传输线脉冲)测试曲线比较SCR与传统ESD结构的优势与劣势并建立SCR在被ESD脉冲触发到折回(Snapback)时的物理模型,然后介绍5 V器件的ESD设计窗口以及SCR结构直接用于5V芯片所存在的问题,如:触发电压过高,闩锁效应(Latch up),误触发等。并通过器件仿真获得I-V特性曲线。在提出多种抗闩锁SCR的同时,给出一种新型SCR结构,该结构不但能够用于泄放I/O口的ESD,同时能在保证VDD到GND的ESD路径不存在闩锁风险的同时泄放ESD电流。文章的最后,对先进的ESD技术进行了介绍,介绍了主动触发电路的概念,并提出一种可抗闩锁效应的SCR触发电路,利用电路仿真软件spectre对其进行了仿真验证,分析。最后,在低压射频(RF)ESD保护领域,通过RFLDMOS项目介绍了低压射频ESD的技术要求,根据TLP测试结果提出了器件优化方案。
[Abstract]:With the development of integrated circuit manufacturing technology, the size of chip becomes smaller and smaller, which brings about the rapid improvement of chip speed and performance, and it is more easily damaged by electrostatic release of (ElectroStatic discharge, (ESD) pulse at the same time. At present, about 30% of the chip failures in the semiconductor industry are caused by ESD, which results in billions of dollars of losses caused by ESD every year. ESD may cause two kinds of problems on chips, one is that direct damage results in loss of function of chips. The damage can be detected during production. The other is the non-fatal damage to the internal circuit of the chip, which can not be detected in production. However, with the increase of the user's time, the performance of the chip becomes unstable, which leads to the decrease of the life span and affects the reputation of the company. Therefore, the design of qualified ESD protection structure is the key to improve the product rate and establish the company's reputation. In this paper, the ESD protection of IC in 5V process is studied, and the problems of SCR (Silicon Controlled Rectifier, thyristor rectifier used in ESD protection of 5V IC are studied and the SCR structure is optimized. In this paper, the theory of ESD protection and common ESD protection devices, such as diode, BJT,GGNMOS,SCR., are briefly introduced. The advantage and disadvantage of SCR and traditional ESD structure are compared by TLP (Transmission Line Pulse, transmission line pulse) test curve, and the physical model of SCR is established when it is triggered by ESD pulse to return to (Snapback). Then the paper introduces the ESD design window of 5V device and the problems existing in the SCR structure directly used in 5V chip, such as high trigger voltage, latch effect (Latch up), mistrigger and so on. The I-V characteristic curve is obtained by device simulation. At the same time, a new type of SCR structure is proposed, which can not only be used to release the ESD, of I / O port, but also can discharge ESD current without latch risk in the ESD path from VDD to GND. At the end of the paper, the advanced ESD technology is introduced, the concept of active trigger circuit is introduced, and a SCR trigger circuit which can resist latch effect is proposed. The circuit simulation software spectre is used to verify and analyze it. Finally, in the field of low-voltage RF (RF) ESD protection, the technical requirements of low-voltage RF ESD are introduced through the RFLDMOS project, and the device optimization scheme is proposed according to the test results of TLP.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN405
本文编号：2295480
[Abstract]:With the development of integrated circuit manufacturing technology, the size of chip becomes smaller and smaller, which brings about the rapid improvement of chip speed and performance, and it is more easily damaged by electrostatic release of (ElectroStatic discharge, (ESD) pulse at the same time. At present, about 30% of the chip failures in the semiconductor industry are caused by ESD, which results in billions of dollars of losses caused by ESD every year. ESD may cause two kinds of problems on chips, one is that direct damage results in loss of function of chips. The damage can be detected during production. The other is the non-fatal damage to the internal circuit of the chip, which can not be detected in production. However, with the increase of the user's time, the performance of the chip becomes unstable, which leads to the decrease of the life span and affects the reputation of the company. Therefore, the design of qualified ESD protection structure is the key to improve the product rate and establish the company's reputation. In this paper, the ESD protection of IC in 5V process is studied, and the problems of SCR (Silicon Controlled Rectifier, thyristor rectifier used in ESD protection of 5V IC are studied and the SCR structure is optimized. In this paper, the theory of ESD protection and common ESD protection devices, such as diode, BJT,GGNMOS,SCR., are briefly introduced. The advantage and disadvantage of SCR and traditional ESD structure are compared by TLP (Transmission Line Pulse, transmission line pulse) test curve, and the physical model of SCR is established when it is triggered by ESD pulse to return to (Snapback). Then the paper introduces the ESD design window of 5V device and the problems existing in the SCR structure directly used in 5V chip, such as high trigger voltage, latch effect (Latch up), mistrigger and so on. The I-V characteristic curve is obtained by device simulation. At the same time, a new type of SCR structure is proposed, which can not only be used to release the ESD, of I / O port, but also can discharge ESD current without latch risk in the ESD path from VDD to GND. At the end of the paper, the advanced ESD technology is introduced, the concept of active trigger circuit is introduced, and a SCR trigger circuit which can resist latch effect is proposed. The circuit simulation software spectre is used to verify and analyze it. Finally, in the field of low-voltage RF (RF) ESD protection, the technical requirements of low-voltage RF ESD are introduced through the RFLDMOS project, and the device optimization scheme is proposed according to the test results of TLP.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN405
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