HS32K芯片工程批流片的后端实现
发布时间:2018-10-26 15:14
【摘要】:在集成电路迅猛发展的今天,SOC芯片逐渐成为业界的焦点。SOC设计流程主要是从前端设计到后端实现,设计周期一般都会很长。前端设计主要包括RTL代码的编译;门级网表综合;静态时序分析。后端实现主要包括整体布局布线;功耗分析;物理验证。如今工艺尺寸已经进入超深亚微米阶段。时间延迟、信号完整性、天线效应等问题已经越发严重,它们制约着当今集成电路的发展。本文针对上述三个问题进行了深入研究,提出了解决方案并且成功应用到了HS32K芯片的物理设计中。HS32K芯片采用HJTC的110nm工艺,工作电压为1.5V,工作电流为30m A。论文主要通过Design Compiler、IC Compiler、Prime Time等工具分析时序、功耗、拥塞度等各方面问题。本文基于HS32K芯片的物理设计,介绍了该款芯片后端实现的整体流程。对物理环境建立、布局规划、IO和标准单元布局、时钟树综合、布线设计等关键步骤作出了详细分析。基于传统方法进行静态时序分析,对每个关键步骤的时序都严格验证。在时钟树综合之后,采用useful_skew修复建立时间违例。得到GDSII文件和网表文件后,通过时序、预期功能的检验;DRC、LVS检查并完成天线效应的修复。最终实现HS32K的工程批流片。本文中的主要工作包括如下:在时钟树综合之后,大胆采用useful_skew方法修复建立时间违例,得到了很好的效果。布线完成后,仍有两条shorting问题,切除附近少许电源网格来增加布线通道,利用IC Compiler工具自动绕线,成功修复了这两条shorting问题。
[Abstract]:With the rapid development of integrated circuits, SOC chips have gradually become the focus of the industry. The design process of SOC is mainly from front-end design to back-end implementation, and the design cycle is usually very long. Front-end design mainly includes RTL code compilation, gate network table synthesis, static timing analysis. The back-end implementation mainly includes overall layout and routing, power analysis and physical verification. Now the process size has entered the ultra-deep sub-micron stage. The problems of time delay, signal integrity and antenna effect have become more and more serious, which restrict the development of integrated circuits. In this paper, the above three problems are deeply studied, and the solution is put forward and successfully applied to the physical design of HS32K chip. The HS32K chip adopts the 110nm technology of HJTC, the working voltage is 1.5V and the working current is 30mA. In this paper, Design Compiler,IC Compiler,Prime Time and other tools are used to analyze timing, power consumption, congestion and other problems. Based on the physical design of the HS32K chip, this paper introduces the whole process of the backend implementation of the chip. The key steps such as physical environment establishment, layout planning, IO and standard cell layout, clock tree synthesis, routing design and so on are analyzed in detail. The static timing analysis based on the traditional method is verified strictly for each key step. After clock tree synthesis, useful_skew is used to repair the time violation. After the GDSII file and the network table file are obtained, the time sequence and expected function are checked, and the antenna effect is checked and repaired by DRC,LVS. Finally, the project batch flow sheet of HS32K is realized. The main work of this paper is as follows: after clock tree synthesis, useful_skew method is used to repair the establishment time violation and good results are obtained. After wiring is completed, there are still two shorting problems. The two shorting problems are successfully repaired by removing a few power grids nearby to increase the wiring channel and using the IC Compiler tool to automatically wrap the wire.
【学位授予单位】:辽宁大学
【学位级别】:硕士
【学位授予年份】:2015
【分类号】:TN405
本文编号:2296132
[Abstract]:With the rapid development of integrated circuits, SOC chips have gradually become the focus of the industry. The design process of SOC is mainly from front-end design to back-end implementation, and the design cycle is usually very long. Front-end design mainly includes RTL code compilation, gate network table synthesis, static timing analysis. The back-end implementation mainly includes overall layout and routing, power analysis and physical verification. Now the process size has entered the ultra-deep sub-micron stage. The problems of time delay, signal integrity and antenna effect have become more and more serious, which restrict the development of integrated circuits. In this paper, the above three problems are deeply studied, and the solution is put forward and successfully applied to the physical design of HS32K chip. The HS32K chip adopts the 110nm technology of HJTC, the working voltage is 1.5V and the working current is 30mA. In this paper, Design Compiler,IC Compiler,Prime Time and other tools are used to analyze timing, power consumption, congestion and other problems. Based on the physical design of the HS32K chip, this paper introduces the whole process of the backend implementation of the chip. The key steps such as physical environment establishment, layout planning, IO and standard cell layout, clock tree synthesis, routing design and so on are analyzed in detail. The static timing analysis based on the traditional method is verified strictly for each key step. After clock tree synthesis, useful_skew is used to repair the time violation. After the GDSII file and the network table file are obtained, the time sequence and expected function are checked, and the antenna effect is checked and repaired by DRC,LVS. Finally, the project batch flow sheet of HS32K is realized. The main work of this paper is as follows: after clock tree synthesis, useful_skew method is used to repair the establishment time violation and good results are obtained. After wiring is completed, there are still two shorting problems. The two shorting problems are successfully repaired by removing a few power grids nearby to increase the wiring channel and using the IC Compiler tool to automatically wrap the wire.
【学位授予单位】:辽宁大学
【学位级别】:硕士
【学位授予年份】:2015
【分类号】:TN405
【参考文献】
相关期刊论文 前2条
1 周平,戴庆元;芯片设计中串扰噪声的分析与改善[J];半导体技术;2004年01期
2 时昕,王东辉,侯朝焕;深亚微米SoC中的电源/地网络设计[J];微电子学与计算机;2004年12期
,本文编号:2296132
本文链接:https://www.wllwen.com/kejilunwen/dianzigongchenglunwen/2296132.html