应用于硅基成像阵列的毫米波宽带分频器研究与芯片设计

发布时间：2018-11-02 18:10

【摘要】：毫米波宽带分频器作为毫米波频率综合器中的关键模块之一,用于对VCO的输出信号进行分频从而获得稳定的本振信号。其性能极大地影响整个毫米波频率综合器性能,因此设计高速、低功耗、分频比可变的分频器具有重要的意义。根据ALMA Bandl(31.3～45GHz)硅基成像阵列锁相环频率综合器的系统指标要求,锁相环应工作在27.3-33GHz频率范围内,输入参考频率设定为50MHz。因此,本文需要设计的毫米波宽带分频器工作频率应覆盖27.3-33GHz,分频比为546-660。为了达到0.1GHz的频率分辨率,本文采用二分频器与可编程分频器级联结构。为了满足毫米波宽带需求本文提出的毫米波宽带分频器由毫米波宽带二分频器和基于脉冲吞咽计数器的可编程分频器组成。本文最后给出了该毫米波宽带分频器在硅基成像阵列锁相环中的应用方案。本文采用90nm CMOS工艺对各芯片进行了电路设计、前仿真、版图设计、后仿真,并进行了流片和测试验证。毫米波宽带二分频器采用两级DCML触发器结构,利用螺旋电感和传输线电感的串联峰化作用对带尾电流源的DCML分频器和Razavi结构DCML分频器进行了设计改进,提高了输入灵敏度,并通过优化电路尺寸和采用伪对称版图设计首次将Razavi结构二分频器的工作频率提高到40GHz。测试结果表明,改进的Razavi结构DCML分频器实现了300MHz～40GHz工作频率、-40dBm输入灵敏度、最低功耗为0.96mmW的高性能毫米波宽带分频,芯片面积为0.51x0.50mm2。基于脉冲吞咽计数器的可编程分频器由8/9双模分频器和可编程脉冲吞咽计数器构成。其中8/9双模分频器采用改进的内嵌或门的CML同步4/5分频器和异步二分频器结构,后仿真结果表明该双模分频器能够工作在10-20GHz；最低输入电压幅度为50mV.功耗最低仅为3.84mW。可编程脉冲吞咽计数器采用改进的带置数功能的TSPC D触发器,提高了计数器工作速度。测试结果表明,该可编程分频器工作频率为7-20.5GHz；分频比为16～519；核心电路功耗为8.52mW；输入灵敏度为-23dBm：芯片面积为0.575×0.475mm2。在改进的Razavi结构DCML毫米波宽带二分频器和基于脉冲吞咽计数器的可编程分频器研究的基础上,本文设计了一款25-37GHz毫米波宽带分频器,测试结果表明：该毫米波宽带分频器分频比为32～1038；当工作频率为37GHz、频偏为1MHz时的相位噪声低于-130dBc/Hz,灵敏度优于-20dBm,动态功耗为17.88mW：芯片面积为0.730x0.475mm2。同时将其应用于基于CP的ALMA Band 1硅基成像阵列锁相环中,测试结果表明：该锁相环工作的最高工作频率达34.027GHz,当分频比为556时,在1MHz频偏处的相位噪声为-91.332dBc/Hz、3MHz频偏处的相位噪声为-107.612dBc/Hz。该锁相环功耗为30.72mW,芯片面积为1.32x1.01mm2。综上,本文设计的毫米波宽带分频器可用于ALMA Band1硅基成像阵列锁相环以及其它毫米波频率综合器中。
[Abstract]:As one of the key modules of millimeter-wave frequency synthesizer, millimeter-wave wideband frequency divider is used to divide the output signal of VCO to obtain stable local oscillator signal. Its performance greatly affects the performance of the whole millimeter-wave frequency synthesizer, so it is of great significance to design a frequency divider with high speed, low power consumption and variable frequency division ratio. According to the system requirements of ALMA Bandl (31.3~45GHz) silicon imaging array PLL frequency synthesizer, PLL should work in the 27.3-33GHz frequency range, the input reference frequency is set to 50MHz. Therefore, the working frequency of the millimeter wave wideband frequency divider to be designed in this paper should cover 27.3-33 GHz, and the frequency division ratio is 546-660. In order to achieve the frequency resolution of 0.1GHz, a cascade structure of two frequency divider and programmable frequency divider is adopted in this paper. In order to meet the requirement of millimeter-wave broadband, the millimeter-wave frequency divider proposed in this paper consists of a millimeter-wave wideband frequency divider and a programmable divider based on pulse swallowing counter. Finally, the application scheme of the millimeter wave wideband frequency divider in silicon based imaging array PLL is presented. In this paper, the circuit design, pre-simulation, layout design, post-simulation, flow sheet and test verification of each chip are carried out by using 90nm CMOS process. The millimeter-wave wideband frequency divider adopts two-stage DCML flip-flop structure. The DCML divider with tail current source and the DCML divider with Razavi structure are designed and improved by using the series peak action of spiral inductor and transmission line inductor, and the input sensitivity is improved. By optimizing the circuit size and using pseudo-symmetric layout, the frequency of Razavi divider is increased to 40 GHz for the first time. The test results show that the improved DCML divider with Razavi structure realizes the 300MHz~40GHz frequency, the input sensitivity of 40dBm, and the minimum power dissipation is 0.96mmW. The chip area is 0.51x0.50mm2. The programmable divider based on pulse swallowing counter is composed of 8 / 9 dual mode frequency divider and programmable pulse swallowing counter. The 8 / 9 dual-mode divider uses an improved CML synchronous 4 / 5 frequency divider and an asynchronous dicusser structure. The simulation results show that the dual-mode divider can work at 10-20 GHz and the minimum input voltage amplitude is 50 MV. The lowest power consumption is only 3.84 MW. The programmable pulse swallowing counter adopts the improved TSPC D flip-flop with the function of number setting, which improves the working speed of the counter. The test results show that the frequency of the programmable divider is 7-20.5 GHz, the frequency division ratio is 16519, the power consumption of the core circuit is 8.52 MW, the input sensitivity is -23dBmand, the chip area is 0.575 脳 0.475mm2m2. Based on the research of the improved Razavi DCML millimeter wave wideband frequency divider and the programmable frequency divider based on pulse swallowing counter, a 25-37GHz millimeter wave wideband frequency divider is designed in this paper. The test results show that the frequency division ratio of the millimeter-wave wideband frequency divider is 32 / 1038. When the operating frequency is 37GHz and the frequency offset is 1MHz, the phase noise is lower than -130dBc / Hz, the sensitivity is better than -20dBm, the dynamic power consumption is 17.88mW, and the chip area is 0.730x0.475mm ~ 2. At the same time, it is applied to the ALMA Band _ 1 silicon-based imaging array phase-locked loop based on CP. The test results show that the highest working frequency of the PLL is 34.027 GHz, and the phase noise at the 1MHz frequency offset is -91.332 dBc / Hz when the frequency division ratio is 556. The phase noise at the frequency offset of 3MHz is -107.612 dBc / Hz. The power consumption of the PLL is 30.72 MW and the chip area is 1.32 x 1.01mm-2. In summary, the millimeter-wave wideband frequency divider designed in this paper can be used in ALMA Band1 silicon-based imaging array PLL and other millimeter-wave frequency synthesizers.
【学位授予单位】：东南大学
【学位级别】：博士
【学位授予年份】：2015
【分类号】：TN772;TN402

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