12位带数字校准的SAR ADC设计与实现
发布时间：2018-11-06 07:30
【摘要】：在纳米工艺节点下,为了满足系统要求驱动模数转换器(ADC)向高速、高精度和低功耗领域发展。由于SAR ADC具有低功耗、结构简单、易集成等优点成为研究的热点。为满足高精度应用需求,本文主要研究了在12位SAR ADC中数字校准算法,为减小采样电容的面积开销及输入负载本文采用分裂电容阵列的电容DAC。影响SAR ADC线性度的主要是电容失配,针对这个问题本论文在自校准算法的基础上提出了改进算法。改进算法节省了1/4的电容开销,可以直接利用数字电路对误差电压进行校准,取得了较好的校准效果。针对低功耗的要求,在对比分析了4种开关方式后,选择能效最好的单片开关方式,相对于传统的开关方式这种方法可以节省81%的功耗开销。另外,论文详细分析了分裂电容结构原理,为改善线性度,本文设计了衰减电容为整数电容的两段式电容阵列。最后论文通过MATLAB建模的方式确定了关键电路模块的指标,本文详细分析关键电路模块原理。最后基于分裂电容阵列的数字校准算法设计实现了一个12位采样速率为500KSPs的带数字校准的SAR ADC。版图后仿结果表明该ADC获得输入频率为奈奎斯特频率有效精度11.2位,功耗为1mW,FoM值为5.6pJ/conv-step,在相似的工作条件下Analog Devices公司AD7892系列产品功耗为60mW。
[Abstract]:In order to meet the requirements of the system, (ADC) drives the development of high speed, high precision and low power consumption in nanotechnology nodes. Because of its advantages of low power consumption, simple structure and easy integration, SAR ADC has become a research hotspot. In order to meet the demand of high precision application, this paper mainly studies the digital calibration algorithm in 12-bit SAR ADC. In order to reduce the area overhead of sampling capacitance and input load, this paper adopts the capacitor DAC. of split capacitor array. The linear degree of SAR ADC is mainly affected by capacitor mismatch. In this paper, an improved algorithm based on self-calibration algorithm is proposed. The improved algorithm saves a quarter of the capacitor overhead and can be calibrated directly by using digital circuits to calibrate error voltages, and good calibration results are obtained. According to the requirement of low power consumption, after comparing and analyzing the four switching modes, the single chip switch with the best energy efficiency can save 81% of power consumption compared with the traditional switching method. In addition, the structure principle of split capacitor is analyzed in detail. In order to improve the linearity, a two-segment capacitor array is designed, in which the attenuation capacitance is an integer capacitance. Finally, the key circuit module is determined by MATLAB modeling method, and the principle of the key circuit module is analyzed in detail. Finally, a digital calibration algorithm based on split capacitor array is designed to implement a 12-bit SAR ADC. with digital calibration with 500KSPs sampling rate. The simulation results after layout show that the input frequency of the ADC is 11.2-bit effective precision of Nyquist frequency, the power consumption is 5.6pJ / conv-step. the power consumption of Analog Devices's AD7892 series products is 60mW under similar working conditions.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN792
本文编号：2313567
[Abstract]:In order to meet the requirements of the system, (ADC) drives the development of high speed, high precision and low power consumption in nanotechnology nodes. Because of its advantages of low power consumption, simple structure and easy integration, SAR ADC has become a research hotspot. In order to meet the demand of high precision application, this paper mainly studies the digital calibration algorithm in 12-bit SAR ADC. In order to reduce the area overhead of sampling capacitance and input load, this paper adopts the capacitor DAC. of split capacitor array. The linear degree of SAR ADC is mainly affected by capacitor mismatch. In this paper, an improved algorithm based on self-calibration algorithm is proposed. The improved algorithm saves a quarter of the capacitor overhead and can be calibrated directly by using digital circuits to calibrate error voltages, and good calibration results are obtained. According to the requirement of low power consumption, after comparing and analyzing the four switching modes, the single chip switch with the best energy efficiency can save 81% of power consumption compared with the traditional switching method. In addition, the structure principle of split capacitor is analyzed in detail. In order to improve the linearity, a two-segment capacitor array is designed, in which the attenuation capacitance is an integer capacitance. Finally, the key circuit module is determined by MATLAB modeling method, and the principle of the key circuit module is analyzed in detail. Finally, a digital calibration algorithm based on split capacitor array is designed to implement a 12-bit SAR ADC. with digital calibration with 500KSPs sampling rate. The simulation results after layout show that the input frequency of the ADC is 11.2-bit effective precision of Nyquist frequency, the power consumption is 5.6pJ / conv-step. the power consumption of Analog Devices's AD7892 series products is 60mW under similar working conditions.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN792
【参考文献】
相关期刊论文 前2条
1 佟星元;;模/数转换器结构设计综述[J];西安邮电大学学报;2013年02期
2 周文婷;李章全;;SAR A/D转换器中电容失配问题的分析[J];微电子学;2007年02期
，本文编号：2313567
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