基于多FPGA的电力电子半实物仿真系统研究
发布时间：2018-11-06 15:16
【摘要】：大功率复杂电力电子装置通常需要半实物仿真系统来加速装置开发和功能验证。然而,商业化电力电子半实物仿真系统均由国外公司垄断,价格昂贵,系统升级维护费用高,开放性差,仿真容量和接口数量也受限;国内针对电力电子半实物仿真系统的开发也较少。为此,本文对适用于电力电子领域的半实物仿真系统展开了研究。解析了半实物仿真系统的工作原理,本文对当前常见半实物仿真系统的架构及性能进行了对比和分析。综合其优点,本文给出了一种基于多FPGA的电力电子半实物仿真系统架构。将半实物仿真系统的各功能模块独立开来,形成不同功能板卡,方便系统扩容;采用全硬件FPGA架构,以多片FPGA作为并行核心运算单元,有效增加了系统仿真容量,缩短了仿真步长,保障了系统的仿真精度。针对本文半实物仿真系统,分析了该架构设计时的关键技术问题。首先分析了电力电子实时仿真对计算资源的要求,其次对多FPGA的级联拓扑进行了对比选取,定义了各板卡间的通信结构并对各功能板卡间数据实时传输需求进行了分析,并设计了一种满足以上通信需求的增强型SPI通信方式,实现了接口板卡与FPGA核心计算板卡间的数据通信;采用LVDS高速通信实现扩容FPGA核心计算板卡间的数据交换。基于以上分析,本文搭建了基于多FPGA的电力电子半实物仿真平台,给出了平台的具体设计过程,并从仿真容量及精度上对其性能进行了估算与分析。最后采用硬件描述语言搭建了10kV 12级联H桥STATCOM电路模型,载入FPGA核心计算板卡中,将外部控制器与半实物仿真平台相连接,实现了10kV STATCOM的硬件在回路闭环仿真控制。同时搭建了5级联小功率H桥STATCOM平台对半实物仿真系统进行了更深一步的对比测试。实验结果表明:仿真步长2us时,半实物仿真与Matlab仿真误差0.5%以内;系统可以长时间稳定的对理想状况和非理想状况工作的电力电子装置进行半实物仿真,通过半实物仿真验证的控制器可以直接应用于实际平台。
[Abstract]:High power complex power electronic devices usually need hardware-in-the-loop simulation system to accelerate device development and function verification. However, the commercial power electronic hardware-in-the-loop simulation systems are monopolized by foreign companies, the price is high, the cost of system upgrade and maintenance is high, the openness is poor, the simulation capacity and the number of interfaces are also limited. The domestic development of power electronic hardware-in-the-loop simulation system is also less. Therefore, the hardware-in-the-loop simulation system suitable for power electronics is studied in this paper. The working principle of the hardware-in-the-loop simulation system is analyzed and the structure and performance of the current hardware-in-the-loop simulation system are compared and analyzed in this paper. Combining its advantages, this paper presents a power electronics hardware-in-the-loop simulation system architecture based on multiple FPGA. The functional modules of the hardware-in-the-loop simulation system are separated to form different functional boards to facilitate the expansion of the system. With the full hardware FPGA architecture and multi-chip FPGA as the parallel core operation unit, the system simulation capacity is increased effectively, the simulation step is shortened, and the simulation accuracy is guaranteed. The key technical problems in the design of this architecture are analyzed for the hardware-in-the-loop simulation system in this paper. Firstly, the requirements of power electronic real-time simulation for computing resources are analyzed. Secondly, the cascade topology of multiple FPGA is compared and selected, and the communication structure among boards is defined, and the requirement of real-time data transmission between functional boards is analyzed. An enhanced SPI communication mode is designed to meet the above communication requirements, and the data communication between the interface board and the FPGA core computing board is realized. LVDS high-speed communication is used to realize the data exchange between the core computing boards of expanded FPGA. Based on the above analysis, the power electronics hardware-in-the-loop simulation platform based on multi-FPGA is built, the design process of the platform is given, and its performance is estimated and analyzed in terms of simulation capacity and accuracy. Finally, the STATCOM circuit model of 10kV 12 cascaded H bridge is built by using hardware description language, which is loaded into the core computing board of FPGA. The external controller is connected with the hardware-in-the-loop simulation platform, and the hardware in loop closed-loop simulation control of 10kV STATCOM is realized. At the same time, a 5 cascade low power H bridge STATCOM platform is built to further test the hardware-in-the-loop simulation system. The experimental results show that the error between hardware-in-the-loop simulation and Matlab simulation is less than 0.5% when the simulation step is 2us. The system can be used to simulate the power electronic devices working in ideal and non-ideal conditions for a long time and the controller can be directly applied to the real platform through the hardware-in-the-loop simulation.
【学位授予单位】：南京航空航天大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TN791;TP391.9
本文编号：2314659
[Abstract]:High power complex power electronic devices usually need hardware-in-the-loop simulation system to accelerate device development and function verification. However, the commercial power electronic hardware-in-the-loop simulation systems are monopolized by foreign companies, the price is high, the cost of system upgrade and maintenance is high, the openness is poor, the simulation capacity and the number of interfaces are also limited. The domestic development of power electronic hardware-in-the-loop simulation system is also less. Therefore, the hardware-in-the-loop simulation system suitable for power electronics is studied in this paper. The working principle of the hardware-in-the-loop simulation system is analyzed and the structure and performance of the current hardware-in-the-loop simulation system are compared and analyzed in this paper. Combining its advantages, this paper presents a power electronics hardware-in-the-loop simulation system architecture based on multiple FPGA. The functional modules of the hardware-in-the-loop simulation system are separated to form different functional boards to facilitate the expansion of the system. With the full hardware FPGA architecture and multi-chip FPGA as the parallel core operation unit, the system simulation capacity is increased effectively, the simulation step is shortened, and the simulation accuracy is guaranteed. The key technical problems in the design of this architecture are analyzed for the hardware-in-the-loop simulation system in this paper. Firstly, the requirements of power electronic real-time simulation for computing resources are analyzed. Secondly, the cascade topology of multiple FPGA is compared and selected, and the communication structure among boards is defined, and the requirement of real-time data transmission between functional boards is analyzed. An enhanced SPI communication mode is designed to meet the above communication requirements, and the data communication between the interface board and the FPGA core computing board is realized. LVDS high-speed communication is used to realize the data exchange between the core computing boards of expanded FPGA. Based on the above analysis, the power electronics hardware-in-the-loop simulation platform based on multi-FPGA is built, the design process of the platform is given, and its performance is estimated and analyzed in terms of simulation capacity and accuracy. Finally, the STATCOM circuit model of 10kV 12 cascaded H bridge is built by using hardware description language, which is loaded into the core computing board of FPGA. The external controller is connected with the hardware-in-the-loop simulation platform, and the hardware in loop closed-loop simulation control of 10kV STATCOM is realized. At the same time, a 5 cascade low power H bridge STATCOM platform is built to further test the hardware-in-the-loop simulation system. The experimental results show that the error between hardware-in-the-loop simulation and Matlab simulation is less than 0.5% when the simulation step is 2us. The system can be used to simulate the power electronic devices working in ideal and non-ideal conditions for a long time and the controller can be directly applied to the real platform through the hardware-in-the-loop simulation.
【学位授予单位】：南京航空航天大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TN791;TP391.9
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