用于加速度计中的单环四阶∑△调制器设计

发布时间：2018-11-06 16:08

【摘要】：随着微电子工艺和技术的发展,高精度的模数转换器(ADC)在民用市场和军事领域的应用越来越广泛。对于加速度传感器而言,基于Sigma-Delta(ΣΔ)调制技术的数字闭环接口电路对器件失配的敏感度较低,易于和数字芯片集成,是实现高性能加速度计接口电路的有效途径之一。作为加速度计接口电路中关键模块的ΣΔ调制器是制约其性能的主要瓶颈之一。本文针对高性能加速度计接口电路的应用需求,完成高精度的ΣΔ调制器电路的研究和设计。本文首先比较了几种低通ΣΔ调制器的特点,选择了一种四阶单环的全前馈结构作为本文的设计目标。该结构能够减小积分器的输出摆幅,不仅降低了整体功耗,还有利于减小系统的谐波失真。在Matlab的Simulink环境下对该系统建立非理想行为级模型,其中包含运放非理想模型、开关非理想模型、运放热噪声模型、KT/C噪声模型等等。通过建模仿真优化确定结构参数以及运放等模块的设计参数,为后级电路设计提供基础。基于系统的量化噪声传递函数和量化器的准线性模型,利用根轨迹法对该高阶系统的稳定性进行分析。通过非理想行为级建模确定设计参数后,在Spectre下对该调制器进行模块电路的设计,包括积分器、比较器、开关电容求和电路、时钟产生电路、一位DAC电路等等。为了抑制偶次谐波失真和共模干扰,采用全差分结构进行电路设计。全差分运放的共模反馈环路采用开关电容电路实现,降低共模反馈环路对输出摆幅和运放直流增益的影响。采用斩波稳定技术来降低第一级积分器运放1/f噪声和失调对调制器输出的影响。基于标准的0.5μm CMOS工艺进行整体仿真,调制器电路在1kHz带宽内信噪比为102dB,与行为级建模仿真结果相近,系统的动态范围约为105dB。完成了版图的设计、后仿真验证以及初步的测试工作。版图的后仿真结果和电路仿真结果相接近。测试结果表明,在5V电源电压下,采样频率为250kHz时,系统功耗为20mW。其中,不带斩波技术的调制器电路信噪比为89dB,带斩波技术的调制器电路信噪比达到99dB,验证了斩波技术原理的正确性,完成了预期的设计目标。
[Abstract]:With the development of microelectronic technology, high precision ADC (ADC) is widely used in civil market and military field. For the acceleration sensor, the digital closed-loop interface circuit based on Sigma-Delta (危螖) modulation technology is less sensitive to device mismatch and easy to integrate with digital chip. It is one of the effective ways to realize the interface circuit of high performance accelerometer. 危螖 modulator, which is the key module of accelerometer interface circuit, is one of the main bottlenecks to its performance. In order to meet the application requirement of high performance accelerometer interface circuit, the high precision 危螖 modulator circuit is studied and designed in this paper. In this paper, the characteristics of several low-pass 危螖 modulators are compared, and a four-order single-ring full-feedforward structure is chosen as the design objective of this paper. The structure can reduce the output swing of the integrator, which not only reduces the overall power consumption, but also helps to reduce the harmonic distortion of the system. In the Simulink environment of Matlab, the non-ideal behavioral level model of the system is established, which includes the non-ideal model of operational amplifier, the non-ideal model of switch, the noise model of operational heat release, the model of KT/C noise and so on. The structural parameters and the design parameters of the operational amplifier module are optimized by modeling and simulation, which provides the basis for the design of the lower stage circuit. Based on the quantization noise transfer function of the system and the quasilinear model of the quantizer, the stability of the high-order system is analyzed by the root locus method. After the design parameters are determined by non-ideal behavior level modeling, the modulator is designed under Spectre, including integrator, comparator, switched-capacitor summation circuit, clock generation circuit, one-bit DAC circuit and so on. In order to suppress even harmonic distortion and common-mode interference, a fully differential circuit is designed. The common-mode feedback loop of fully differential operational amplifier is realized by switched capacitor circuit to reduce the effect of common-mode feedback loop on output swing and DC gain of operational amplifier. The chopper stabilization technique is used to reduce the effect of the 1- / f noise and misalignment of the first stage integrator on the output of the modulator. The whole simulation based on the standard 0.5 渭 m CMOS process shows that the signal-to-noise ratio of the modulator circuit is 102 dB in the 1kHz bandwidth, which is close to the simulation result of the behavioral level modeling. The dynamic range of the system is about 105 dB. Completed layout design, post-simulation verification and preliminary testing work. The post-simulation results of layout are close to those of circuit simulation. The test results show that the power consumption of the system is 20 MW when the sampling frequency is 250kHz. The signal-to-noise ratio of the modulator circuit without chopping technique is 89 dB, and the signal-to-noise ratio of the modulator circuit with chopper technology is 99dB, which verifies the correctness of chopping technology and accomplishes the expected design goal.
【学位授予单位】：齐齐哈尔大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN761

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