面向退化效应的组合电路测试通路选择算法研究
发布时间：2018-11-07 16:13
【摘要】：测试在集成电路的设计、生产和制造过程中都扮演着十分重要的作用。对于组合逻辑电路,需要对其内部各条通路上的时延进行测试,判断电路是否满足时序要求。然而随着电路规模的不断增大,电路中通路的数量也急剧增长,难以对全部通路进行时延测试,需要在电路所有通路中选择出延迟最大的关键通路,通过检测关键通路的延时情况对电路时序状态给出评价。然而随着集成电路特征尺寸的降低和电路结构的日益复杂,退化效应对电路的影响越来越大。退化效应对电路内各门单元器件的时延情况产生影响,从而影响电路中每条通路上的时延,进而造成在电路生命周期中的不同时刻存在不同的关键通路。因此本文重点分析退化效应对组合电路时序造成的影响,根据电路延迟的变化情况,自适应的选择合适的关键通路进行时延测试,从而提高关键通路选择的准确性和时延测试的有效性。本文将组合电路退化行为与时延测试通路进行结合,解决了在退化效应影响下的时延测试通路的搜寻问题。从典型退化效应机理研究出发,在分析组合电路内基本门单元的退化行为的基础上,研究门单元内退化与时延变化的关系,建立电路内门单元时延变化与退化效应的关系。以此为基础,利用拓扑图思想对电路结构进行建模,获取电路内各器件单元的互联关系,进而建立组合电路测试通路选择问题的数学模型。在获取的时延信息、老化时延信息以及互联信息的基础上,采取贪婪算法中的深度优先搜索算法完成对电路关键通路的搜索工作,验证了在电路生命周期内,关键通路会由于退化效应的影响而发生变化。为了解决深度优先搜索算法在大规模电路测试通路选择中搜索效率低、速度慢的问题,本文利用蚁群算法,在尽可能保证通路搜索准确率的条件下提高关键通路的搜索效率。实验结果表明,两种算法都能够完成退化效应下组合电路时延测试的关键通路搜索,并且蚁群优化算法在一定程度上,提高了在考虑退化效应下的关键通路搜寻的效率。
[Abstract]:Testing plays an important role in the design, production and manufacture of integrated circuits. For combinational logic circuits, it is necessary to test the time delay in each path to determine whether the circuit meets the timing requirements. However, with the increasing of circuit scale, the number of paths in the circuit increases rapidly, so it is difficult to test the delay of all the paths, so it is necessary to select the key path with the largest delay in all the circuit paths. The timing state of the circuit is evaluated by detecting the delay of the critical path. However, with the decreasing of the feature size and the increasing complexity of the circuit structure, the degradation effect is becoming more and more important. The degradation effect has an effect on the delay of each gate element in the circuit, thus affecting the delay on each path in the circuit, which leads to the existence of different critical paths at different times in the circuit life cycle. Therefore, this paper focuses on analyzing the effect of degradation effect on the timing of combinational circuits. According to the variation of circuit delay, we adaptively select the appropriate key path to test the time delay. In order to improve the accuracy of critical path selection and the effectiveness of delay testing. In this paper, the degradation behavior of combinational circuits is combined with the delay test path to solve the problem of searching the delay test path under the influence of degradation effect. Based on the analysis of the degradation behavior of the basic gate cells in the combinational circuits, the relationship between the degradation and the delay changes in the gate cells is studied, and the relationship between the delay changes and the degradation effects of the gate cells in the circuit is established based on the study of the mechanism of the typical degradation effect. On this basis, the topology idea is used to model the circuit structure, to obtain the interconnection of each device unit in the circuit, and then to establish the mathematical model of the test path selection problem of the combinational circuit. On the basis of the acquired delay information, aging delay information and interconnection information, the depth first search algorithm of greedy algorithm is adopted to complete the searching work of the critical circuit path, which verifies that in the circuit life cycle, the key path of the circuit is searched. The key pathways change as a result of the degradation effect. In order to solve the problem of low searching efficiency and slow speed of depth first search algorithm in large-scale circuit test path selection, this paper uses ant colony algorithm to improve the search efficiency of critical path under the condition that the accuracy of path search is guaranteed as much as possible. The experimental results show that both of the two algorithms can search the critical path for the delay test of combinational circuits under the degradation effect, and the ant colony optimization algorithm improves the efficiency of the key path search considering the degradation effect to a certain extent.
【学位授予单位】：哈尔滨工业大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN407
本文编号：2316879
[Abstract]:Testing plays an important role in the design, production and manufacture of integrated circuits. For combinational logic circuits, it is necessary to test the time delay in each path to determine whether the circuit meets the timing requirements. However, with the increasing of circuit scale, the number of paths in the circuit increases rapidly, so it is difficult to test the delay of all the paths, so it is necessary to select the key path with the largest delay in all the circuit paths. The timing state of the circuit is evaluated by detecting the delay of the critical path. However, with the decreasing of the feature size and the increasing complexity of the circuit structure, the degradation effect is becoming more and more important. The degradation effect has an effect on the delay of each gate element in the circuit, thus affecting the delay on each path in the circuit, which leads to the existence of different critical paths at different times in the circuit life cycle. Therefore, this paper focuses on analyzing the effect of degradation effect on the timing of combinational circuits. According to the variation of circuit delay, we adaptively select the appropriate key path to test the time delay. In order to improve the accuracy of critical path selection and the effectiveness of delay testing. In this paper, the degradation behavior of combinational circuits is combined with the delay test path to solve the problem of searching the delay test path under the influence of degradation effect. Based on the analysis of the degradation behavior of the basic gate cells in the combinational circuits, the relationship between the degradation and the delay changes in the gate cells is studied, and the relationship between the delay changes and the degradation effects of the gate cells in the circuit is established based on the study of the mechanism of the typical degradation effect. On this basis, the topology idea is used to model the circuit structure, to obtain the interconnection of each device unit in the circuit, and then to establish the mathematical model of the test path selection problem of the combinational circuit. On the basis of the acquired delay information, aging delay information and interconnection information, the depth first search algorithm of greedy algorithm is adopted to complete the searching work of the critical circuit path, which verifies that in the circuit life cycle, the key path of the circuit is searched. The key pathways change as a result of the degradation effect. In order to solve the problem of low searching efficiency and slow speed of depth first search algorithm in large-scale circuit test path selection, this paper uses ant colony algorithm to improve the search efficiency of critical path under the condition that the accuracy of path search is guaranteed as much as possible. The experimental results show that both of the two algorithms can search the critical path for the delay test of combinational circuits under the degradation effect, and the ant colony optimization algorithm improves the efficiency of the key path search considering the degradation effect to a certain extent.
【学位授予单位】：哈尔滨工业大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN407
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，本文编号：2316879
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