基于FPGA的光时域反射仪信号采集系统设计

发布时间：2018-11-10 06:50

【摘要】：OTDR（Optical Time Domain Reflectometer，光时域反射仪）是一种光纤测量专用仪器，它根据瑞利散射测算出光纤延长度的损耗信息，根据菲涅尔反射定位光纤事件位置，，是光纤通信领域不可缺少的测量和维护设备。目前，OTDR除了要具备大动态范围、小盲区、高分辨率等性能，还要具备较强的数据交换能力以及较快的数据处理能力。信号采集系统作为OTDR主要组成部分，承担着OTDR返回光信号的采集、存储、传输、处理的重要功能。随着实际工程对OTDR的性能要求越来越高，OTDR对信号采集系统也提出了更高的要求。本文在对数据采集技术以及OTDR原理的研究基础上，结合OTDR的发展需要，以实现信号高速采集、数据高无缝速存储和传输、改善信噪比为目标，提出一种基于FPGA的光时域反射仪信号采集系统。该系统以Altera公司的FPGA芯片EP4CE40F23C8N作为核心控制芯片，利用高性能低功耗模数转换芯片AD9230进行快速数字化，考虑了采集系统数据存储和数据传输高速和实时的需要，利用两片SRAM存储器ISSI61LV25616通过乒乓操作进行数据存储，同时结合USB接口高速数据吞吐的优势，使用USB数据线实现与上位机的数据传递，最终实现光时域反射仪信号采集系统。本系统由硬件与软件共同组成。系统硬件设计包括FPGA核心电路模块、信号接收与调理电路模块、模数转换电路模块、数据存储电路模块、USB接口电路模块、时钟晶振与电源电路模块，本文对各模块的设计思路和电路进行了介绍。系统软件设计包括下位机FPGA逻辑功能设计和上位机信号线性累加处理。其中，FPGA逻辑功能设计部分分为AD控制模块、FIFO缓冲模块、存储控制模块、USB接口控制模块等，本文从状态转换、逻辑功能等方面对各个模块进行了说明，并应用Modelsim软件对各个模块进行了功能仿真。信号线性累加处理部分介绍了算法主要流程，应用Matlab软件设计了图型显示界面并实现了线性累加算法的仿真。
[Abstract]:OTDR (Optical Time Domain Reflectometer, optical time domain reflectometer (OTDR) is a special optical fiber measurement instrument, which calculates the loss information of fiber extension according to Rayleigh scattering, and locates the location of optical fiber event according to Fresnel reflection. Is an indispensable measurement and maintenance equipment in the field of optical fiber communication. At present, OTDR not only has large dynamic range, small blind area, high resolution and so on, but also has strong data exchange ability and fast data processing ability. As the main component of OTDR, the signal acquisition system is responsible for the important functions of OTDR signal acquisition, storage, transmission and processing. With the higher performance requirements of OTDR in practical engineering, OTDR also puts forward higher requirements for signal acquisition system. Based on the research of data acquisition technology and OTDR principle, combined with the development needs of OTDR, this paper aims to achieve high-speed signal acquisition, high-speed storage and transmission of data, and improve signal-to-noise ratio (SNR). A signal acquisition system for optical time domain reflectometer based on FPGA is proposed. In this system, the FPGA chip EP4CE40F23C8N of Altera Company is used as the core control chip, and the high performance and low power A / D conversion chip AD9230 is used for fast digitization. The requirement of high speed and real time data storage and data transmission in the acquisition system is considered. Two pieces of SRAM memory ISSI61LV25616 are used to store data through ping-pong operation. At the same time, combined with the advantage of high-speed data throughput of USB interface, the data transfer between PC and PC is realized by using USB data line. Finally, the signal acquisition system of optical time domain reflectometer is realized. The system is composed of hardware and software. The system hardware design includes FPGA core circuit module, signal receiving and conditioning circuit module, analog-to-digital conversion circuit module, data storage circuit module, USB interface circuit module, clock crystal oscillator and power supply circuit module. The design idea and circuit of each module are introduced in this paper. The software design of the system includes the logic function design of the lower computer FPGA and the linear accumulative processing of the upper computer signal. Among them, FPGA logic function design is divided into AD control module, FIFO buffer module, storage control module, USB interface control module, etc. The function of each module is simulated by Modelsim software. In the part of signal linear accumulation processing, the main flow of the algorithm is introduced. The graphic display interface is designed by using Matlab software and the simulation of linear accumulation algorithm is realized.
【学位授予单位】：太原理工大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TP274.2;TN791

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