异构多核系统调试技术的研究与实现

发布时间：2018-11-20 18:42

【摘要】：随着半导体制造工艺的快速发展以及集成电路设计技术的不断提高,传统的单核SoC架构已经无法满足日益增长的性能需求,多核SoC技术应运而生。相较于同构多核系统,异构多核系统能够实现资源的最优化配置,在处理复杂特定任务时具有更大的优势。然而,异构多核系统的出现,导致软硬件设计的正确性验证更加困难,没有硬件支持的调试技术已经无法胜任这些复杂的应用。因此,在芯片中采用可调试性设计逐渐成为一种提高芯片调试效率的重要手段,并得到学术界和工业界的广泛研究。本文针对上述问题,开展了异构多核系统调试技术的相关研究。论文的主要工作如下：首先,基于课题组设计完成的一款异构多核系统,设计并实现了一种可配置可裁剪的可调试性模型,为目标系统芯片的生产及实际应用提供有力的支持。可调试性模型包括片上调试架构和上位机软件两部分,本文的工作重点是目标系统可调试性设计的硬件部分,即片上调试架构的设计与实现。其次,对片上调试架构中调试探测器DP的设计进行深入研究,详细分析了目标系统中不同资源节点的调试方案以及相应DP的配置,证明了DP设计的灵活性,同时完成了目标系统中各类资源节点DP模块的电路设计工作。此外,还给出了各DP在FPGA上实现的面积开销,论述了本设计的有效性。最后,将DP模块集成于目标系统中,从RTL级和FPGA两个层次验证了本文设计的DP功能的正确性。此外,通过一个分步调试的应用实例,论述了本文的可调试性设计模型可以通过不同模式的任意组合,快速定位错误所在,有效地支持目标系统的调试工作。本文实现的可调试性设计模型在对目标系统的调试控制方面具有如下特点：(1)采取“离线”调试方案,即预先设定断点或触发点,待系统执行触发调试后,暂停原执行过程进入调试态,获取相关调试数据之后再恢复系统运行。(2)提供五种不同的调试模式以满足目标系统实际应用的调试需求,每次可以根据需选择一种模式生成调试控制命令。(3)调试单元采用模块化设计,对其作相应的功能裁剪,即可实现针对系统中不同资源节点的可调试性设计。(4)调试单元具有可配置性,通过配置各控制寄存器,灵活地设置断点或观察点。
[Abstract]:With the rapid development of semiconductor manufacturing process and the continuous improvement of integrated circuit design technology, the traditional single-core SoC architecture can no longer meet the increasing performance requirements, and the multi-core SoC technology emerges as the times require. Compared with isomorphic multicore systems, heterogeneous multicore systems can achieve optimal allocation of resources and have greater advantages in dealing with complex and specific tasks. However, due to the emergence of heterogeneous multi-core systems, it is more difficult to verify the correctness of hardware and software design, and the debugging technology without hardware support can not be used in these complex applications. Therefore, the use of debug design in chips has gradually become an important means to improve the efficiency of chip debugging, and has been widely studied by academia and industry. In order to solve the above problems, this paper studies the debugging technology of heterogeneous multi-core system. The main work of this paper is as follows: firstly, based on a heterogeneous multi-core system designed by the research group, a configurable and tailor-made debug model is designed and implemented, which provides a powerful support for the production and practical application of the target system chip. The debug model includes two parts: on-chip debugging architecture and host computer software. The emphasis of this paper is the hardware part of the debug design of the target system, that is, the design and implementation of the on-chip debugging architecture. Secondly, the design of debug detector DP in the on-chip debugging architecture is studied, and the debugging scheme of different resource nodes in the target system and the configuration of corresponding DP are analyzed in detail, which proves the flexibility of DP design. At the same time, the circuit design of various resource node DP modules in the target system is completed. In addition, the area overhead realized by DP on FPGA is given, and the effectiveness of this design is discussed. Finally, the DP module is integrated into the target system, and the correctness of the DP function designed in this paper is verified from the RTL level and the FPGA level. In addition, through an application example of step debugging, it is discussed that the debugging design model of this paper can quickly locate the error by any combination of different modes, and effectively support the debugging work of the target system. The Debuggability Design Model realized in this paper has the following characteristics in debugging and controlling the target system: (1) the off-line debugging scheme is adopted, that is, the breakpoint or trigger point is set in advance, and after the system executes the trigger debugging, Pause the original execution process into debugging state, obtain relevant debugging data before resuming the system. (2) provide five different debugging modes to meet the debugging needs of the actual application of the target system. According to the need to select a mode to generate debug control commands. (3) the debugging unit is designed by modularization, and the corresponding function is clipped. Debuggability design for different resource nodes in the system can be realized. (4) Debug unit is configurable and can set breakpoint or observation point flexibly by configuring each control register.
【学位授予单位】：合肥工业大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN402

【相似文献】