多通道高速时钟数据恢复电路设计
发布时间：2018-11-26 10:07
【摘要】：随着通信技术的高速发展,超级计算机、智能终端和多媒体网络等海量数据的快速传输,用户对数据的传输提出了更高的要求。由于串行通信高速率的优点,使其逐渐成为接口的主流技术。IEEE 802.3ae协议定义了一种高速的、灵活的信号传输模式。采用多通道的XAUI(10 Ggigbit Attachment Unit Interface)接口,对信号进行8/10 bit编码,完成10 Gbps数据通信。CDR(Clock and Data Recovery)是串行通信技术领域最关键的电路,也是高速接口速率提升的瓶颈,工作在协议的物理层部分,完成时钟的生成和数据的重定时,对整个通信系统的性能起到了决定性作用。本文基于标准SMIC 0.13μm CMOS工艺,采用自顶向下的设计方法,不断对CDR环路和单元电路进行优化,完成四通道、总有效数据率为10 Gbps的高速C DR电路设计。本课题的主要内容是:1)对PI(Phase Interpolator)电路进行详细的理论分析。把PI的权重因子分为线性的和非线性的分别讨论,找到一种非线性的权重因子可以使PI输出信号的相位有很好的线性度。同时,讨论了PI输入信号的上升时间、输入信号的相位差和输出节点的时间常数三者相互作用对PI线性度的影响。2)本次CDR电路根据XAUI接口标准选择四个通道,每个通道共享PLL电路提供的参考时钟。采用模拟正交相位插值结构的CDR电路,既提高了PI最小相位跳跃精度,又适用于高速电路。电路设计时,先对环路进行适当的改进,加入了差分转单端电路,减小了恢复时钟的峰峰值抖动。然后,根据单元电路设计需求,鉴相器选择半速率的Alexander鉴相器,电荷泵选择全差分结构,并把PI电路的电阻负载改进为对称负载。CDR电路版图的面积为532μm*426μm。单通道输入伪随机序列码的长度为223-1,数据的波特率为3.125 Gbps。仿真结果表明:在SS工艺角下锁定时间为6.2μs,恢复的时钟信号峰峰值抖动为28.8μs,功耗最大在FF的工艺角下为17.2 mW,满足设计要求。
[Abstract]:With the rapid development of communication technology and the rapid transmission of massive data such as supercomputers, intelligent terminals and multimedia networks, users have put forward higher requirements for data transmission. Because of the high speed of serial communication, it has gradually become the mainstream technology of interface. IEEE 802.3ae protocol defines a high speed and flexible signal transmission mode. Using the multi-channel XAUI (10 Ggigbit Attachment Unit Interface) interface) to encode the signal with 8 / 10 bit and complete the 10 Gbps data communication. CDR (Clock and Data Recovery) is the most important circuit in the field of serial communication technology, and it is also the bottleneck of increasing the speed of high-speed interface. Working in the physical layer of the protocol, clock generation and data retiming play a decisive role in the performance of the whole communication system. Based on the standard SMIC 0.13 渭 m CMOS process, the top-down design method is used to optimize the circuit of CDR loop and unit continuously, and to complete the design of high-speed C DR circuit with four channels and a total effective data rate of 10 Gbps. The main contents of this paper are as follows: 1) theoretical analysis of PI (Phase Interpolator) circuit is carried out in detail. The weight factor of PI is divided into linear and nonlinear, and a nonlinear weight factor is found to make the phase of PI output signal have good linearity. At the same time, the influence of the rise time of the PI input signal, the phase difference of the input signal and the time constant of the output node on the linearity of the PI is discussed. 2) the CDR circuit selects four channels according to the XAUI interface standard. Each channel shares the reference clock provided by the PLL circuit. The CDR circuit with analog orthogonal phase interpolation not only improves the minimum phase jump accuracy of PI, but also is suitable for high speed circuits. When the circuit is designed, the loop is improved properly and the differential switching circuit is added to reduce the peak and peak jitter of the recovery clock. Then, according to the design requirements of the cell circuit, the phase discriminator selects the Alexander phase detector with half rate and the charge pump selects the fully differential structure. The resistive load of the PI circuit is improved to a symmetrical load. The area of the CDR circuit layout is 532 渭 m ~ 426 渭 m. The length of single-channel input pseudorandom sequence code is 223-1, and the baud rate of data is 3.125 Gbps.. The simulation results show that the locking time is 6.2 渭 s at the SS process angle, the peak jitter of the recovered clock signal is 28.8 渭 s, and the maximum power consumption is 17.2 mW, at the FF process angle.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN402
，
本文编号：2358247
[Abstract]:With the rapid development of communication technology and the rapid transmission of massive data such as supercomputers, intelligent terminals and multimedia networks, users have put forward higher requirements for data transmission. Because of the high speed of serial communication, it has gradually become the mainstream technology of interface. IEEE 802.3ae protocol defines a high speed and flexible signal transmission mode. Using the multi-channel XAUI (10 Ggigbit Attachment Unit Interface) interface) to encode the signal with 8 / 10 bit and complete the 10 Gbps data communication. CDR (Clock and Data Recovery) is the most important circuit in the field of serial communication technology, and it is also the bottleneck of increasing the speed of high-speed interface. Working in the physical layer of the protocol, clock generation and data retiming play a decisive role in the performance of the whole communication system. Based on the standard SMIC 0.13 渭 m CMOS process, the top-down design method is used to optimize the circuit of CDR loop and unit continuously, and to complete the design of high-speed C DR circuit with four channels and a total effective data rate of 10 Gbps. The main contents of this paper are as follows: 1) theoretical analysis of PI (Phase Interpolator) circuit is carried out in detail. The weight factor of PI is divided into linear and nonlinear, and a nonlinear weight factor is found to make the phase of PI output signal have good linearity. At the same time, the influence of the rise time of the PI input signal, the phase difference of the input signal and the time constant of the output node on the linearity of the PI is discussed. 2) the CDR circuit selects four channels according to the XAUI interface standard. Each channel shares the reference clock provided by the PLL circuit. The CDR circuit with analog orthogonal phase interpolation not only improves the minimum phase jump accuracy of PI, but also is suitable for high speed circuits. When the circuit is designed, the loop is improved properly and the differential switching circuit is added to reduce the peak and peak jitter of the recovery clock. Then, according to the design requirements of the cell circuit, the phase discriminator selects the Alexander phase detector with half rate and the charge pump selects the fully differential structure. The resistive load of the PI circuit is improved to a symmetrical load. The area of the CDR circuit layout is 532 渭 m ~ 426 渭 m. The length of single-channel input pseudorandom sequence code is 223-1, and the baud rate of data is 3.125 Gbps.. The simulation results show that the locking time is 6.2 渭 s at the SS process angle, the peak jitter of the recovered clock signal is 28.8 渭 s, and the maximum power consumption is 17.2 mW, at the FF process angle.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN402
，
本文编号：2358247
本文链接：https://www.wllwen.com/kejilunwen/dianzigongchenglunwen/2358247.html
