基于改进量子进化算法的3D NoC测试TSV优化
发布时间：2018-12-07 12:39
【摘要】：针对硅通孔(through-silicon-via,TSV)的生产成本高,占用面积大等问题,首先对三维片上网络(3D NoC)进行测试规划研究,将测试规划得到的最短测试时间作为约束条件,采用改进的量子进化算法优化测试占用的TSV数量,将各层的TSV按照需求进行配置,并将TSV合理有效地分配给各个内核,以在有限的TSV数量下,降低硬件开销,提高利用率,同时,探讨TSV的分配对测试时间的影响。算法中,引入量子旋转门旋转角动态调整策略和量子变异策略,以提高算法的全局寻优能力和收敛速度,避免陷入局部最优解。将ITC’02基准电路作为仿真实验对象,由实验结果可得,本算法能够快速地收敛到最佳解,有效的减小了测试时间,优化了TSV数量,提高了TSV的利用率。
[Abstract]:Aiming at the problems of high production cost and large area occupied by silicon through hole (through-silicon-via,TSV), the test planning of 3D NoC is carried out firstly, and the shortest test time obtained from the test planning is taken as the constraint condition. The improved quantum evolutionary algorithm is used to optimize the amount of TSV consumed by the test, and the TSV of each layer is configured according to the requirements, and the TSV is allocated to each kernel reasonably and effectively, so as to reduce the hardware overhead and improve the utilization ratio under the limited TSV number. At the same time, the effect of TSV on the test time was discussed. In order to improve the global optimization ability and convergence speed of the algorithm, quantum rotation gate rotation angle dynamic adjustment strategy and quantum mutation strategy are introduced to avoid falling into the local optimal solution. The ITC'02 reference circuit is taken as the object of simulation experiment. From the experimental results, the algorithm can quickly converge to the optimal solution, effectively reduce the test time, optimize the number of TSV, and improve the utilization rate of TSV.
【作者单位】： 桂林电子科技大学电子工程与自动化学院;广西自动检测技术与仪器重点实验室;
【基金】：国家自然科学基金(61561012) 广西自然科学基金(2014GXNSFAA118398)资助项目
【分类号】：TN407;TP18
本文编号：2367220
[Abstract]:Aiming at the problems of high production cost and large area occupied by silicon through hole (through-silicon-via,TSV), the test planning of 3D NoC is carried out firstly, and the shortest test time obtained from the test planning is taken as the constraint condition. The improved quantum evolutionary algorithm is used to optimize the amount of TSV consumed by the test, and the TSV of each layer is configured according to the requirements, and the TSV is allocated to each kernel reasonably and effectively, so as to reduce the hardware overhead and improve the utilization ratio under the limited TSV number. At the same time, the effect of TSV on the test time was discussed. In order to improve the global optimization ability and convergence speed of the algorithm, quantum rotation gate rotation angle dynamic adjustment strategy and quantum mutation strategy are introduced to avoid falling into the local optimal solution. The ITC'02 reference circuit is taken as the object of simulation experiment. From the experimental results, the algorithm can quickly converge to the optimal solution, effectively reduce the test time, optimize the number of TSV, and improve the utilization rate of TSV.
【作者单位】： 桂林电子科技大学电子工程与自动化学院;广西自动检测技术与仪器重点实验室;
【基金】：国家自然科学基金(61561012) 广西自然科学基金(2014GXNSFAA118398)资助项目
【分类号】：TN407;TP18
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