BDI型红外焦平面读出电路的设计与实现

发布时间：2018-12-07 19:09

【摘要】：红外焦平面阵列作为红外成像系统的关键器件,已经被广泛运用于多种探测领域。红外焦平面阵列主要由红外探测器阵列及读出电路组成,读出电路是连接红外探测器阵列和信号处理系统的主要枢纽,其性能好坏直接影响红外成像系统的应用,高性能的读出电路是红外成像质量的关键所在。本论文主要设计了一款BDI型红外读出电路芯片,首先对红外读出电路涉及的关键参数进行了重点分析,研究了几种不同的像素单元结构的注入效率、动态范围以及线性度的影响因素。由于在版图面积及探测器偏置电压方面的限制,传统的像素单元结构不能直接用于本文的电路架构中,因此,本文对传统的像素单元电路结构进行改进,去掉了传统电路结构中的采样电容,并加入开关控制管,从而更加有效地控制红外探测器的偏置电压。在此基础上,对读出电路的列处理单元及输出缓冲器等模块电路进行了详细设计,两者均采用带米勒补偿的两级运放作为电路的基本结构单元,以实现更大的输出摆幅及更高的电压传输精度。最后基于CSMC 0.5μm CMOS工艺进行了版图设计和流片实验。测试结果表明：所设计芯片电荷容量为80.53Me,动态范围为84.61dB,线性度为98%,功耗为56mmW,输出摆幅为3.4V,基本满足设计要求。
[Abstract]:As the key device of infrared imaging system, infrared focal plane array (IRFPA) has been widely used in many detection fields. The infrared focal plane array is mainly composed of the infrared detector array and the readout circuit. The readout circuit is the main hub connecting the infrared detector array and the signal processing system, and its performance directly affects the application of the infrared imaging system. High performance readout circuit is the key to infrared imaging quality. In this paper, a BDI type infrared readout circuit chip is designed. Firstly, the key parameters of the infrared readout circuit are analyzed, and the injection efficiency of several different pixel cell structures is studied. The influence factors of dynamic range and linearity. Because of the limitation of layout area and detector bias voltage, the traditional pixel cell structure can not be directly used in the circuit architecture of this paper, therefore, the traditional pixel cell circuit structure is improved in this paper. The sampling capacitance in the traditional circuit structure is removed and the switch control tube is added to control the bias voltage of the infrared detector more effectively. On this basis, the column processing unit and output buffer module circuit of readout circuit are designed in detail. Both of them adopt two-stage operational amplifier with Hans Muller compensation as the basic structure unit of the circuit. In order to achieve greater output swing and higher voltage transmission accuracy. Finally, layout design and flow sheet experiment are carried out based on CSMC 0.5 渭 m CMOS process. The test results show that the designed chip has a charge capacity of 80.53 Me, a dynamic range of 84.61 dB, a linearity of 98 and a power consumption of 56mmW, and an output swing of 3.4 V, which basically meets the design requirements.
【学位授予单位】：东南大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN215

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