基于TFET器件模型的单元特性仿真

发布时间：2018-12-23 19:54

【摘要】：随着集成电路的蓬勃发展,市场对低功耗器件需求日趋严重,业界对其中最具发展前景的隧穿场效应晶体管(Tunnel Field-Effect Transistor,TFET)的研究也在不断深入。国内外最新研究表明,TFET工艺制作周期短、工作电压低,通过量子隧穿效应产生电流,这与传统MOSFET依赖载流子漂移扩散形成电流的方式不同。这种独特的器件结构使TFET的静态功耗非常小,预示着TFET在低功耗器件领域有很大的应用市场。本文目标是完成基于TFET器件模型的单元特性仿真工作。论文在比较了TFET和传统MOSFET的电学特性和导电机制之后,选取20 nm工艺下III-V族异质结半导体化合物结构的TFET器件模型,并对基于该TFET模型的标准单元进行了参数仿真。仿真对象包括反相器、与非门、或与非门和动态D触发器等,仿真的参数包括传播延时、输出传输时间、短路能耗和静态功耗。结果显示,复杂逻辑门的单个输入的传播延时和一个TFET基本反相器延时相同,这与逻辑努力的理论相吻合。测量D触发器时序参数,结果表明该动态D触发器具有极小的建立、保持时间,电路性能较高。同时论文对基于该TFET器件模型的三种不同结构的静态存储器进行了仿真。仿真内容包括读噪声容限和写噪声容限。第一和第二种TFET静态存储器的读噪声容限和写噪声容限效果不理想,第三种静态存储器在前两种的基础上进行了结构的调整,得到的读噪声容限128.1 m V,写噪声容限55.3 m V,较好的满足了静态存储器读稳定性和写稳定性的要求。仿真结果在理论上证明了在静态存储器设计中TFET单元代替传统MOSFET单元的可行性。由于单元特性仿真的参数并未涉及到寄生参数信息,故本文可视为对TFET器件模型的基础性研究,为后继TFET器件代替传统MOSFET器件的技术研究方向提供一定的参考价值。
[Abstract]:With the rapid development of integrated circuits, the demand for low-power devices is becoming more and more serious, and the research on tunneling field effect transistors (Tunnel Field-Effect Transistor,TFET), which have the most promising prospect, is also getting deeper and deeper. The latest studies at home and abroad show that TFET process has short fabrication period and low working voltage, which is different from the traditional mode of MOSFET dependent carrier drift diffusion to generate current through quantum tunneling effect. This unique device structure makes the static power consumption of TFET very small, which indicates that TFET has a large application market in the field of low-power devices. The aim of this paper is to complete the simulation of cell characteristics based on TFET device model. After comparing the electrical properties and conductive mechanism between TFET and traditional MOSFET, the TFET device model of III-V heterojunction semiconductor compound structure under 20 nm process is selected, and the standard cell based on the TFET model is simulated. The simulation objects include inverter, non-gate, or non-gate and dynamic D flip-flop. The simulation parameters include propagation delay, output transmission time, short-circuit energy consumption and static power consumption. The results show that the propagation delay of a single input of the complex logic gate is the same as that of a TFET basic inverter, which is consistent with the theory of logic effort. The time series parameters of D flip-flop are measured. The results show that the dynamic D flip-flop has minimal establishment, holding time and high circuit performance. At the same time, three kinds of static memory based on the TFET device model are simulated. The simulation includes read noise tolerance and write noise tolerance. The read noise tolerance and write noise tolerance of the first and second TFET static memory are not ideal. The third static memory is adjusted on the basis of the first two, and the read noise tolerance is 128.1 MV. The write noise tolerance is 55.3 MV, which meets the requirements of the static memory read stability and write stability. The simulation results demonstrate the feasibility of replacing the traditional MOSFET cells with TFET cells in the static memory design. Because the parameters of cell characteristic simulation do not involve parasitic parameter information, this paper can be regarded as the basic research of TFET device model, which provides a certain reference value for the following TFET device to replace the traditional MOSFET device technology research direction.
【学位授予单位】：哈尔滨工业大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN386

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