低杂散双环频率合成器的研制

发布时间：2018-12-29 21:33

【摘要】：频率合成技术广泛应用于通信、雷达、电子对抗、卫星发射以及收发系统中,各个系统的高性能可否实现,频率合成模块是其决定因素之一。随着通信领域的高速发展,传统晶振已难以满足当前的需求,频率合成器的指标要求也随之提高,并且不同的领域,对具体的要求又有所不同。比如,在通信系统,要求低杂散性能;在电子对抗系统中,要求快速的频率切换;在雷达系统中,要求极低的噪声;而在另外的系统中,则又可能要求小步进或者宽的频率覆盖。在本文中,首先,分析了DDS技术以及PLL技术的基本理论;然后,结合自身频率合成设计经验,着重的分析DDS与PLL的劣势性能及其改善方法;最后,结合项目具体的指标要求,设计出小数锁相环与整数锁相环混频的双环结构。双环输出进行上变频处理,充分利用小数锁相环的步进与整数锁相环的频率覆盖。在此基础上,较为创新的提出可变参考源方案,将小数杂散移至环路带宽外,依靠环路的窄带滤波特性,实现频率合成器的高杂散性能。双环结构通过器件的合理选型,在Hittite PLL design的仿真,论证方案可行性。最终测试结果表明,该方案能够实现6~7GHz的频率覆盖,杂散抑制达到70dBc,相位噪声-95dBc/Hz@1KHz,-100dBc/Hz@10KHz。
[Abstract]:Frequency synthesis technology is widely used in communication, radar, electronic countermeasures, satellite transmission and transceiver systems, the high performance of each system can be realized, frequency synthesis module is one of its determinants. With the rapid development of the communication field, the traditional crystal oscillator has been difficult to meet the current demand, and the requirements of frequency synthesizer are also increased, and the specific requirements are different in different fields. For example, in communication system, low spurious performance is required; in electronic countermeasure system, fast frequency switching is required; in radar system, very low noise is required. In other systems, a small step or wide frequency coverage may be required. In this paper, the basic theory of DDS technology and PLL technology is analyzed firstly, and then the inferior performance of DDS and PLL and their improvement methods are analyzed based on their own experience in frequency synthesis design. Finally, the dual loop structure of decimal PLL and integer PLL is designed according to the specific requirements of the project. The double loop output is processed by up-conversion, which makes full use of the step of fractional phase-locked loop and the frequency coverage of integer phase-locked loop. On this basis, a new variable reference source scheme is proposed, which shifts the fractional spurious to the bandwidth of the loop and realizes the high spurious performance of the frequency synthesizer based on the narrow band filter characteristics of the loop. Through the reasonable selection of the device, the double ring structure is simulated in Hittite PLL design, and the feasibility of the scheme is demonstrated. The final test results show that the scheme can achieve the frequency coverage of 6~7GHz, the spurious suppression is up to 70dBc, and the phase noise is -95dBc / Hz-100dBc / HzBc- 100dBc / Hz@ 10kHz.
【学位授予单位】：华中科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN74

【相似文献】