用于TIADC的一种后台校准算法的研究和实现

发布时间：2019-01-24 09:49

【摘要】：如今,数字信号处理技术已然成为了信号处理中最为重要的一项技术,并在通信,雷达,医疗仪器,语音识别等重要领域被广泛应用。模数转换器(ADC)作为用来将模拟信号转换为数字信号的电子元件,在这个数字化技术急速发展的时代中的重要地位日趋明显。但速度与精度之间的矛盾关系严重制约了ADC性能的提高。时间交织模数转换器(TIADC)结构成为了突破瓶颈的重要选择。它采用多个通道并行交替采样的结构,在维持子通道ADC的转换精度不变的情况下,成倍提高了ADC的整体采样率。但是工艺误差会导致TIADC各个通道之间存在失调失配、增益失配和时钟失配,这些失配误差将严重制约交织后整体系统的动态性能。数字校准技术就成为了提升TIADC性能的关键技术。本文首先在TIADC工作原理的基础上针对三种失配建立了系统等效误差模型,在理论层面分析了它们给系统性能造成的影响,并以此为基础对现已有校准算法的适用范围进行了分析。接下来,针对三种失配误差设计了一种基于LMS自适应滤波的全数字后台校准算法。该算法通过改进的变步长LMS自适应滤波器对增益失配和时钟失配误差进行校准,提高了自适应过程的收敛速度,而失调失配则通过指数平均器累加消除。为了验证算法的有效性,本文首先在Matlab/Simulink中以精度10bits,采样率200MHz的Pipeline ADC为子通道建立了5通道TIADC模型,完成了算法的功能设计与验证。并在此基础上用Modelsim对算法的Verilog HDL编码进行了仿真验证。最后,FPGA验证结果表明,当输入频率为29.8MHz,采样频率为1 GHz时,该算法能够将含有失配的TIADC系统有效位数从3.31562bits提升到9.33113bits,将SNR从21.72dB提高到了57.95dB。
[Abstract]:Nowadays, digital signal processing technology has become the most important technology in signal processing, and has been widely used in communication, radar, medical instruments, speech recognition and other important fields. Analog-to-digital converter (ADC), as an electronic component used to convert analog signal into digital signal, is becoming more and more important in the era of rapid development of digital technology. However, the contradiction between speed and precision seriously restricts the improvement of ADC performance. The (TIADC) structure of time interleaved ADC has become an important choice to break through the bottleneck. It adopts a multi-channel parallel alternate sampling structure, which can increase the overall sampling rate of ADC by multiplying the conversion accuracy of the sub-channel ADC. However, the process errors will lead to mismatch, gain mismatch and clock mismatch between TIADC channels. These mismatch errors will seriously restrict the dynamic performance of the whole system after interleaving. Digital calibration technology has become the key technology to improve the performance of TIADC. In this paper, based on the working principle of TIADC, the system equivalent error model is established for three mismatches, and the influence of them on system performance is analyzed theoretically. On this basis, the scope of application of existing calibration algorithms is analyzed. Then, a full digital background calibration algorithm based on LMS adaptive filter is designed for three mismatch errors. The improved variable step size LMS adaptive filter is used to calibrate the gain mismatch and clock mismatch, which improves the convergence rate of the adaptive process, while the offset mismatch is eliminated by the exponential average cumulatively. In order to verify the validity of the algorithm, a five-channel TIADC model is established in Matlab/Simulink with precision of 10 bits and Pipeline ADC of sampling rate 200MHz as the sub-channel, and the function of the algorithm is designed and verified. On this basis, the Verilog HDL coding of the algorithm is simulated with Modelsim. Finally, the FPGA verification results show that when the input frequency is 29.8 MHz and the sampling frequency is 1 GHz, the algorithm can increase the effective bit number of TIADC system with mismatch from 3.31562bits to 9.33113 bits and SNR from 21.72dB to 57.95 dB.
【学位授予单位】：合肥工业大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN792

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