集成电路老化在线预测与检测技术的研究

发布时间：2019-03-17 21:21

【摘要】：随着半导体技术的飞速发展,集成电路的集成度越来越来高,其性能不断提升的同时,其可靠性正面临着巨大的挑战。为确保其能在使用周期内正常运行,使得集成电路老化效应成为可靠性问题的关键。集成电路老化效应会使组合电路延时增加,引起时序错误,最终导致电路功能失效。因此针对集成电路老化效应引起的时序错误,需要寻找有效的测试与防护方法。基于此,本文主要对集成电路老化在线预测与检测技术进行研究。本文首先介绍了集成电路老化效应的机理,同步时序电路的时序约束,并逐步阐述两者的联系,从而清晰的说明了集成电路老化如何引起时序错误,也就是本文研究的核心问题。然后,介绍了基于此问题现有的两种有效测试方法:集成电路老化在线预测技术与集成电路老化在线检测技术。最后分别详细的介绍了两种技术下,所提的测试方法与测试结构单元,分析了它们的原理,优点,缺点。基于预测技术,本文提出了一种用于容忍动态频率变化的稳定性检测器设计。通过原系统时钟构建新的监测区间,利用新设计的稳定性检测器将组合电路违规跳变转化成检测脉冲,最后采集检测脉冲从而发出报警信号。仿真结果表明,该方法可以容忍时钟频率变化,面积开销上具有一定的优势,且将原来的两个浮空节点转化成一个节点,提高了整个稳定性检测器的检测能力。结合两种测试技术,本文提出了考虑预采样的时序错误检测与自恢复方法。利用系统本身时钟在时钟有效沿前后构建一个预采样区间和一个检测区间,并在预采样区间内提前捕获输入信号,最后在检测区间内进行时序错误检测,如果检测电路发出报警信号,电路将会进行自纠错。仿真结果表明,相比于其他的检测结构,该结构在检测速度上平均提高了 3.6倍;同时不需要调整时序,电路就可以实现自纠错与自恢复,且不会降低电路的工作性能。本文所提出的两种测试方法,能够很好的检测集成电路老化引起的时序错误,对于解决集成电路的可靠性问题具有一定的价值。
[Abstract]:With the rapid development of semiconductor technology, the integration of integrated circuits becomes more and more high, and its reliability is facing great challenges while its performance is continuously improved. In order to ensure that the IC can operate normally in service cycle, the aging effect of IC becomes the key to reliability problem. The aging effect of the integrated circuit will increase the delay of the combined circuit, cause the timing error, and finally lead to the failure of the circuit function. Therefore, in view of the timing errors caused by the aging effect of integrated circuits, it is necessary to find effective testing and protection methods. Based on this, the on-line prediction and detection technology of IC aging is studied in this paper. This paper first introduces the mechanism of the aging effect of integrated circuits, the timing constraints of synchronous sequential circuits, and expounds the relationship between them step by step, so as to clearly explain how the aging of integrated circuits causes timing errors. That is, the core of this paper. Then, two effective testing methods are introduced: on-line prediction of IC aging and on-line testing of IC aging. Finally, the proposed test methods and test structure units are introduced in detail under the two technologies, and their principles, advantages and disadvantages are analyzed. Based on prediction technique, a design of stability detector for dynamic frequency change tolerance is proposed in this paper. A new monitoring interval is constructed by using the original system clock, and a new designed stability detector is used to transform the combination circuit violation jump into a detection pulse. Finally, the detection pulse is collected and an alarm signal is sent out. The simulation results show that the proposed method can tolerate the change of clock frequency and has some advantages in area overhead, and the original two floating nodes are transformed into one node, which improves the detection ability of the whole stability detector. Combined with two testing techniques, this paper presents a method of timing error detection and self-recovery considering pre-sampling. The clock of the system is used to construct a pre-sampling interval and a detection interval before and after the clock effectively, and the input signal is captured in advance in the pre-sampling interval. Finally, the timing error detection is carried out in the detection interval. If the detection circuit sends an alarm signal, the circuit will perform self-error correction. The simulation results show that, compared with other detection structures, the detection speed of this structure is increased 3.6 times on average, and the circuit can achieve self-error correction and self-recovery without adjusting the timing, and the performance of the circuit can not be reduced. The two testing methods proposed in this paper can well detect the timing errors caused by the aging of integrated circuits and have certain value in solving the reliability problems of integrated circuits.
【学位授予单位】：合肥工业大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN407

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