基于随机化聚类算法的扫描时钟分组方法
发布时间：2019-03-20 11:20
【摘要】：目前,基于IP(Intellectual Property)复用的片上系统设计方法使得专用集成电路(ASIC,Application Specific Integrated Circuit)的设计效率大幅提高。但这种方法也带来了新的挑战,高性能集成电路的可测性设计(DFT,Design For Testability)就是其中最严峻的部分。本课题主要是实现了一款含有同步与异步时钟域的大规模数字基带芯片的ATPG(Automatic Test Pattern Generation,自动测试图形生成)时钟结构优化设计。对大规模的集成电路测试平台,因其电路复杂性高,要达到非常高的故障覆盖率(fault coverage)是非常困难的。如何在保证故障覆盖率的同时减少测试向量数量,成为减少测试成本的研究热点。本文以数字基带芯片的测试向量生成时的时钟结构为研究对象,以提高故障覆盖率和减少测试向量数量为主要目标,设计了随机化聚类算法应用于生成扫描时钟结构,并提出改进型的错位捕获(staggered LOC)技术产生测试向量。本文的主要研究内容和所取得的成果如下:1.在诸聚类算法中,层次聚类算法具有速度快,算法简单的特点,但是其精度较低。本文在层次聚类算法中引入随机化步骤,使算法运行过程带有随机成分,并在多次运行后挑选优化的结果,弥补了层次聚类算法精确度不足的缺点。使之成为适合对含有同步与异步时钟域的大规模芯片进行时钟分组的算法。2.在stuck-at测试模式下,用随机化聚类算法对时钟域进行分组,得到优化的扫描时钟结构,可以减少跨时钟域传播路径的数量,提高故障覆盖率。3.在延时测试(delay test)模式下,通过随机化聚类算法对时钟域进行分组,将互相之间没有跨时钟域传输路径的异步时钟域划分成一组。在同一捕获窗口(capture window)内利用并行捕获(simultaneous Launch-on-Capture)与改进型错位捕获(staggered capture)技术,对时钟域组进行组内并行,组间串行的测试捕获(launch-capture)方法。可以较大程度减少测试向量数量,缩短机台测试时间。
[Abstract]:At present, the design efficiency of application-specific integrated circuit (ASIC,Application Specific Integrated Circuit) is greatly improved by the method of system-on-a-chip design based on IP (Intellectual Property) multiplexing. But this approach also presents new challenges, and the testability design of high-performance integrated circuits (DFT,Design For Testability) is one of the toughest. In this paper, a large-scale digital baseband chip with synchronous and asynchronous clock domain (ATPG (Automatic Test Pattern Generation, automatic test pattern generation) clock structure optimization design is implemented. For large scale integrated circuit test platform, it is very difficult to achieve very high fault coverage (fault coverage) because of its high circuit complexity. How to reduce the number of test vectors while ensuring fault coverage has become a hot topic to reduce the cost of testing. Taking the clock structure of test vector generation in digital baseband chip as the research object, in order to improve the fault coverage and reduce the number of test vectors as the main goal, a randomized clustering algorithm is designed and applied to generate scan clock structure. An improved dislocation capture (staggered LOC) technique is proposed to generate test vectors. The main contents and achievements of this paper are as follows: 1. Among all clustering algorithms, hierarchical clustering algorithm has the characteristics of fast speed and simple algorithm, but its precision is low. In this paper, the randomization step is introduced into the hierarchical clustering algorithm to make the algorithm run with random components, and the optimization results are selected after many runs, which make up for the shortcomings of the lack of accuracy of the hierarchical clustering algorithm. To make it suitable for clock grouping on large-scale chips with synchronous and asynchronous clock domains. 2. In the stuck-at test mode, the random clustering algorithm is used to group the clock domain, and the optimized scan clock structure is obtained, which can reduce the number of propagation paths across the clock domain and improve the fault coverage. 3. In the delay test (delay test) mode, the asynchronous clock domain, which has no transmission path across the clock domain, is divided into a group by means of randomizing clustering algorithm. In the same acquisition window, parallel capture (simultaneous Launch-on-Capture) and improved dislocation capture (staggered capture) techniques are used to implement intra-group parallelism for clock domain groups and serial test capture (launch-capture) method for inter-group groups in the same acquisition window (capture window). It can greatly reduce the number of test vectors and shorten the test time.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN407
[Abstract]:At present, the design efficiency of application-specific integrated circuit (ASIC,Application Specific Integrated Circuit) is greatly improved by the method of system-on-a-chip design based on IP (Intellectual Property) multiplexing. But this approach also presents new challenges, and the testability design of high-performance integrated circuits (DFT,Design For Testability) is one of the toughest. In this paper, a large-scale digital baseband chip with synchronous and asynchronous clock domain (ATPG (Automatic Test Pattern Generation, automatic test pattern generation) clock structure optimization design is implemented. For large scale integrated circuit test platform, it is very difficult to achieve very high fault coverage (fault coverage) because of its high circuit complexity. How to reduce the number of test vectors while ensuring fault coverage has become a hot topic to reduce the cost of testing. Taking the clock structure of test vector generation in digital baseband chip as the research object, in order to improve the fault coverage and reduce the number of test vectors as the main goal, a randomized clustering algorithm is designed and applied to generate scan clock structure. An improved dislocation capture (staggered LOC) technique is proposed to generate test vectors. The main contents and achievements of this paper are as follows: 1. Among all clustering algorithms, hierarchical clustering algorithm has the characteristics of fast speed and simple algorithm, but its precision is low. In this paper, the randomization step is introduced into the hierarchical clustering algorithm to make the algorithm run with random components, and the optimization results are selected after many runs, which make up for the shortcomings of the lack of accuracy of the hierarchical clustering algorithm. To make it suitable for clock grouping on large-scale chips with synchronous and asynchronous clock domains. 2. In the stuck-at test mode, the random clustering algorithm is used to group the clock domain, and the optimized scan clock structure is obtained, which can reduce the number of propagation paths across the clock domain and improve the fault coverage. 3. In the delay test (delay test) mode, the asynchronous clock domain, which has no transmission path across the clock domain, is divided into a group by means of randomizing clustering algorithm. In the same acquisition window, parallel capture (simultaneous Launch-on-Capture) and improved dislocation capture (staggered capture) techniques are used to implement intra-group parallelism for clock domain groups and serial test capture (launch-capture) method for inter-group groups in the same acquisition window (capture window). It can greatly reduce the number of test vectors and shorten the test time.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN407
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