高精度sigma-delta DAC中数字ASIC的设计
发布时间：2019-03-25 21:36
【摘要】：微机械陀螺数字化是目前惯性传感器系统领域的研究热点之一,数字化的微机械陀螺系统已逐渐成为设计主流。在数字化微机械陀螺系统中,高精度的DAC是其关键模块之一。本论文旨在研究一种专门应用于微机械陀螺系统中的高精度sigma-delta DAC数字前端集成电路(ASIC)设计。本文工作内容包含三个主要模块:数字插值滤波器、sigma-delta调制器、DEM动态单元匹配模块。其中数字插值滤波器采用多级数字滤波器级联结构设计,级联结构中包括两级半带滤波器、CIC补偿滤波器与CIC滤波器,在对传统半带滤波器分析的基础上,提出了一种鲁棒性半带滤波器结构,这种结构对传统半带滤波器传递函数进行了改进,使其幅频特性对滤波器系数敏感程度较低,而且该结构具有硬件电路消耗低、电路工作速度快、功耗低的特点;为了实现数字前端ASIC高精度数字位流输出,给出了一种多位量化级联结构的数字sigma-delta调制器的设计,设计中采用误差反馈结构,通过多级级联实现高精度ASIC数字位流输出,降低损耗;考虑到调制器多位数字量化技术易产生非线性问题,本文还进行了动态匹配单元设计,采用数字加权平均算法(DWA)将调制器输出信号产生的失配噪声转化为白噪声进而通过低通滤波器滤除。在Sigma-Delta DAC数字前端专用集成电路结构实现方面,进行了多种技术的优化。首先,基于采样保持电路,对数字插值滤波器结构进行优化,为了进一步降低功耗,进行先滤波后插值结构设计;在多位量化数字sigma-delta调制器硬件电路结构设计方面,采用MASH1-1-1结构,每一级量化器都采用向下截位的方式进行实现,通过使用移位方式进行乘法操作,以减小电路面积的消耗;在DWA算法硬件结构实现时,基于温度计码,采用循环移位的方式来实现;为了缩减输入数据端口的数量,本文采用串口总线SPI接口,对电路的输入数据进行串并转换。最后,本文对整体数字前端专用集成电路进行了硬件实现,采用Cadence Encounter工具,基于0.35μm CMOS工艺,进行了布局布线,时序优化,完成了整体物理版图的设计、后仿真,并进行了流片,所设计的芯片面积为3.0mm×2.8mm。采用FPGA对所设计整体电路进行了测试验证。实验结果表明,该数字前端专用集成电路信噪比约为143.5dB以上,有效位数约为23.5位。
[Abstract]:The digitization of micro-mechanical gyroscope is one of the hotspots in the field of inertial sensor system at present, and the digital micro-mechanical gyroscope system has gradually become the mainstream of design. In digital micromachined gyroscope system, high precision DAC is one of the key modules. In this paper, a high-precision sigma-delta DAC digital front-end integrated circuit (ASIC) design for MEMS gyroscope system is studied. This paper consists of three main modules: digital interpolation filter, sigma-delta modulator, DEM dynamic unit matching module. The digital interpolation filter is designed by cascading structure of multi-stage digital filter. The cascade structure includes two-stage half-band filter, CIC compensation filter and CIC filter. Based on the analysis of the traditional half-band filter, the digital interpolation filter consists of two-stage half-band filter, CIC compensation filter and CIC filter. A robust half-band filter structure is proposed, which improves the transfer function of the traditional half-band filter, and makes its amplitude-frequency characteristic less sensitive to the filter coefficients, and the structure has low consumption of hardware circuit. The circuit has the characteristics of high speed and low power consumption. In order to realize the high precision digital bit stream output of digital front-end ASIC, the design of a multi-bit quantized cascaded digital sigma-delta modulator is presented. The error feedback structure is used in the design, and the high-precision ASIC digital bit stream output is realized by multi-concatenation. Reduce loss; Considering the nonlinearity of the modulator multi-digit quantization technology, the dynamic matching unit is also designed in this paper. The digital weighted average (DWA) algorithm is used to transform the mismatch noise generated by the modulator's output signal into white noise and then filter it by low-pass filter. In the aspect of Sigma-Delta DAC digital front-end ASIC architecture, a variety of optimization techniques have been carried out. Firstly, the structure of the digital interpolation filter is optimized based on the sampling and holding circuit. In order to reduce the power consumption further, the filter structure is first filtered and then the interpolation structure is designed. In the design of hardware circuit structure of multi-bit quantized digital sigma-delta modulator, MASH1-1-1 structure is adopted, every first-level quantizer is implemented by way of downward truncation, and multiplicative operation is carried out by using shift mode. To reduce the consumption of circuit area; In order to reduce the number of input data ports, the serial bus SPI interface is used to convert the input data of the circuit to serial-parallel conversion, when the hardware structure of the DWA algorithm is implemented, which is based on the thermometer code and the way of cyclic shift, in order to reduce the number of input data ports. Finally, the hardware implementation of the integrated digital front-end ASIC is carried out. Based on the 0.35m CMOS process, the layout and routing of the integrated digital front-end ASIC is carried out by using the Cadence Encounter tool, and the timing optimization is carried out. The whole physical layout is designed, and the post-simulation is carried out. The chip area is 3.0mm 脳 2.8 mm. The whole circuit is tested and verified by FPGA. The experimental results show that the signal-to-noise ratio of the digital front-end ASIC is more than 143.5dB and the effective bit is about 23.5 bits.
【学位授予单位】：哈尔滨工业大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN792
本文编号：2447339
[Abstract]:The digitization of micro-mechanical gyroscope is one of the hotspots in the field of inertial sensor system at present, and the digital micro-mechanical gyroscope system has gradually become the mainstream of design. In digital micromachined gyroscope system, high precision DAC is one of the key modules. In this paper, a high-precision sigma-delta DAC digital front-end integrated circuit (ASIC) design for MEMS gyroscope system is studied. This paper consists of three main modules: digital interpolation filter, sigma-delta modulator, DEM dynamic unit matching module. The digital interpolation filter is designed by cascading structure of multi-stage digital filter. The cascade structure includes two-stage half-band filter, CIC compensation filter and CIC filter. Based on the analysis of the traditional half-band filter, the digital interpolation filter consists of two-stage half-band filter, CIC compensation filter and CIC filter. A robust half-band filter structure is proposed, which improves the transfer function of the traditional half-band filter, and makes its amplitude-frequency characteristic less sensitive to the filter coefficients, and the structure has low consumption of hardware circuit. The circuit has the characteristics of high speed and low power consumption. In order to realize the high precision digital bit stream output of digital front-end ASIC, the design of a multi-bit quantized cascaded digital sigma-delta modulator is presented. The error feedback structure is used in the design, and the high-precision ASIC digital bit stream output is realized by multi-concatenation. Reduce loss; Considering the nonlinearity of the modulator multi-digit quantization technology, the dynamic matching unit is also designed in this paper. The digital weighted average (DWA) algorithm is used to transform the mismatch noise generated by the modulator's output signal into white noise and then filter it by low-pass filter. In the aspect of Sigma-Delta DAC digital front-end ASIC architecture, a variety of optimization techniques have been carried out. Firstly, the structure of the digital interpolation filter is optimized based on the sampling and holding circuit. In order to reduce the power consumption further, the filter structure is first filtered and then the interpolation structure is designed. In the design of hardware circuit structure of multi-bit quantized digital sigma-delta modulator, MASH1-1-1 structure is adopted, every first-level quantizer is implemented by way of downward truncation, and multiplicative operation is carried out by using shift mode. To reduce the consumption of circuit area; In order to reduce the number of input data ports, the serial bus SPI interface is used to convert the input data of the circuit to serial-parallel conversion, when the hardware structure of the DWA algorithm is implemented, which is based on the thermometer code and the way of cyclic shift, in order to reduce the number of input data ports. Finally, the hardware implementation of the integrated digital front-end ASIC is carried out. Based on the 0.35m CMOS process, the layout and routing of the integrated digital front-end ASIC is carried out by using the Cadence Encounter tool, and the timing optimization is carried out. The whole physical layout is designed, and the post-simulation is carried out. The chip area is 3.0mm 脳 2.8 mm. The whole circuit is tested and verified by FPGA. The experimental results show that the signal-to-noise ratio of the digital front-end ASIC is more than 143.5dB and the effective bit is about 23.5 bits.
【学位授予单位】：哈尔滨工业大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN792
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