基于FPGA的H.264解码器研究与设计实现

发布时间：2019-03-28 20:20

【摘要】：随着数字视频技术以及计算机通信技术的迅速发展,视频通信成为了当今的研究重点。在进行视频信号存储传输时,视频编解码算法的选取尤为重要。在对视频信号图像分辨率的要求不断提升的同时,人们对视频解码的实时性也有着很高的要求。因此,设计H.264的实时解码器十分关键,为了实现这一目标。选择FPGA来完成的视频图像解码器的设计实现。首先,本文阐述了视频编解码标准的发展历程以及H.264的解码流程。在深入分析H.264解码流程的基础上,将解码器划分为熵解码器、变换系数解码器、预测数据解码器、块滤波器几大功能模块。其次,重点对熵解码器进行设计优化,提出了一种基于预测结构的双幅值熵解码实现结构。此外,对熵解码器中使用频率很高的前一检测器进行优化,提出了一种非均衡优先前一检测器实现结构。实验结果表明相对传统的实现方式,这种双幅值熵解码器可以缩减26%的运算时间。然后,分别完成了变换系数解码器、预测器、块滤波器的设计实现。变换系数解码器的设计采用了可重构结构实现方式,预测器由帧内预测和帧间预测两部分组成,针对块滤波器实现采用了五级流水的方式。接着,设计了位流缓存器来降低解码器从外部存储器读入数据的频率。此外,针对语法元素解析,采用将复杂状态机分解成子状态机的实现方式。设计了位流分解状态机,该方式不仅可以简化设计流程还可降低解码器功耗的34%。最后,在XC500VFX200t平台上使用ISE13.2自带的综合工具对解码器进行综合仿真。解码器的实现需要占用FPGA约5%的寄存器资源、21%左右的查找表资源、最大动态功耗为157mW、数据吞吐率为960K、最高运行频率为216MHz。将整个解码器置于50MHz的工作条件下进行分析,结果表明,解码一个宏块需要577个时钟周期。对于4CIF(704*576@30fps)格式的H.264Baseline级别视频数据,只需工作在27.4MHz频率下即可完成实时解码。综合分析结果表明,本设计实现能够完全满足H.264Baseline的实时解码需求。
[Abstract]:With the rapid development of digital video technology and computer communication technology, video communication has become the focus of research. When the video signal is stored and transmitted, the selection of video codec algorithm is very important. With the improvement of video signal resolution, the real-time performance of video decoding is also very high. Therefore, the design of H.264 real-time decoder is very important, in order to achieve this goal. Select FPGA to complete the design and implementation of the video image decoder. First, this paper describes the development of video coding and decoding standards and H.264 decoding process. Based on the in-depth analysis of H.264 decoding process, the decoder is divided into entropy decoder, transform coefficient decoder, predictive data decoder and block filter. Secondly, the design and optimization of entropy decoder is emphasized, and a two-amplitude entropy decoding architecture based on prediction structure is proposed. In addition, the former detector with high frequency in entropy decoder is optimized, and an implementation structure of non-equilibrium priority former detector is proposed. The experimental results show that the two-amplitude entropy decoder can reduce the operation time by 26% compared with the traditional implementation method. Then, the design and implementation of transform coefficient decoder, predictor and block filter are completed respectively. The transform coefficient decoder is designed with a reconfigurable structure. The predictor is composed of intra-frame prediction and inter-frame prediction, and five-stage pipelining is used for block filter implementation. Then, a bit stream buffer is designed to reduce the frequency of the decoder reading data from the external memory. In addition, the complex state machine is decomposed into sub-state machine for syntax element parsing. A bit stream decomposition state machine is designed, which not only simplifies the design process but also reduces the power consumption of the decoder by 34%. Finally, the integrated simulation of decoder is carried out on the platform of XC500VFX200t using the integrated tool of ISE13.2. The decoder needs about 5% register resource and 21% lookup table resource in FPGA. The maximum dynamic power consumption is 157 MW, the data throughput rate is 960 K, and the highest running frequency is 216 MHz. The whole decoder is analyzed under the working condition of 50MHz. The results show that it takes 577 clock cycles to decode a macro block. For H.264Baseline-level video data in 4CIF (704*576@30fps) format, real-time decoding can be accomplished only at 27.4MHz frequency. The comprehensive analysis results show that this design can fully meet the real-time decoding requirements of H.264Baseline.
【学位授予单位】：中国科学院研究生院(西安光学精密机械研究所)
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN919.81;TN791

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