基于GTX的JESD204B数据接收接口研究与实现
发布时间：2019-03-31 09:48
【摘要】：高速数据采集在无线通信、医疗影像、高速仪器仪表和雷达等领域占有非常重要的地位。随着数据转换器采集速率的提高,与采集数据串行传输方式相比,传统并行传输方式在降低码间同步难度、减小码间串扰、降低布线复杂度和减小资源消耗等方面渐渐暴露其自身的弱点。当前已有多款集成有JESD204B发送接口的AD芯片问世。JESD204B数据接收接口在这种条件下应运而生。国外虽提供有JESD204B接收接口的商业IP核,但该IP核需要收费。更重要的是,第三方提供的IP核关键部分的逻辑电路以“黑盒”的方式提供,使用者并不了解其中的细节。在国防军工领域直接使用这些“黑盒”电路给国防安全留下了隐患。针对上述情况,本文在研究JESD204B接收接口的原理及结构的基础上,探索JESD204B接收接口在FPGA上的实现。该实现分两大部分展开:首先在研究JESD204B接收接口结构和功能的基础上进行总体设计,分析采用GTX高速收发器实现JESD204B接收接口物理层的可行性,研究链路层实现方案,确定传输层数据格式并给出传输层数据提取方案;接着分析实现JESD204B接收接口的关键问题及解决思路。为了验证设计的JESD204B接收接口的性能,对实现的JESD204B接收接口进行了仿真测试和板级实测。仿真结果表明:1)实现的JESD204B接收接口逻辑功能正确,2)Vivado给出的时序分析报告满足电路工作频率要求。板级实测结果表明实现的JESD204B接收接口功能正确,工作稳定。
[Abstract]:High-speed data acquisition plays an important role in wireless communication, medical imaging, high-speed instrument and radar. With the increase of the acquisition rate of the data converter, compared with the serial transmission mode of the acquisition data, the traditional parallel transmission mode reduces the difficulty of inter-symbol synchronization and the inter-symbol crosstalk. Reduce the complexity of routing and reduce the consumption of resources and other aspects gradually exposed its own weaknesses. At present, there are many AD chips integrated with JESD204B sending interface, and the JESD204B data receiving interface comes into being under this condition. Although foreign countries provide a commercial IP core with a JESD204B receiver interface, the IP core requires a fee. More importantly, the logic circuit of the IP core provided by the third party is provided in a "black box" manner, and the user does not know the details of it. The direct use of these "black box" circuits in the field of national defense and military industry leaves a hidden danger to the security of national defense. In view of the above situation, on the basis of studying the principle and structure of the JESD204B receiving interface, this paper explores the realization of the JESD204B receiving interface on the FPGA. The implementation is divided into two parts: firstly, based on the research of the structure and function of JESD204B receiving interface, the feasibility of using GTX high-speed transceiver to realize the physical layer of JESD204B receiver interface is analyzed, and the implementation scheme of link layer is studied. The data format of the transport layer is determined and the data extraction scheme of the transport layer is given. Then the key problems and solutions of JESD204B receiver interface are analyzed. In order to verify the performance of the designed JESD204B receiver interface, the simulation test and board-level measurement of the implemented JESD204B receiver interface are carried out. The simulation results show that: 1) the logic function of the JESD204B receiver interface is correct; 2) the timing analysis report given by Vivado meets the requirement of the circuit working frequency. The experimental results at the board level show that the function of the JESD204B receiver interface is correct and the operation is stable.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN79
本文编号：2450797
[Abstract]:High-speed data acquisition plays an important role in wireless communication, medical imaging, high-speed instrument and radar. With the increase of the acquisition rate of the data converter, compared with the serial transmission mode of the acquisition data, the traditional parallel transmission mode reduces the difficulty of inter-symbol synchronization and the inter-symbol crosstalk. Reduce the complexity of routing and reduce the consumption of resources and other aspects gradually exposed its own weaknesses. At present, there are many AD chips integrated with JESD204B sending interface, and the JESD204B data receiving interface comes into being under this condition. Although foreign countries provide a commercial IP core with a JESD204B receiver interface, the IP core requires a fee. More importantly, the logic circuit of the IP core provided by the third party is provided in a "black box" manner, and the user does not know the details of it. The direct use of these "black box" circuits in the field of national defense and military industry leaves a hidden danger to the security of national defense. In view of the above situation, on the basis of studying the principle and structure of the JESD204B receiving interface, this paper explores the realization of the JESD204B receiving interface on the FPGA. The implementation is divided into two parts: firstly, based on the research of the structure and function of JESD204B receiving interface, the feasibility of using GTX high-speed transceiver to realize the physical layer of JESD204B receiver interface is analyzed, and the implementation scheme of link layer is studied. The data format of the transport layer is determined and the data extraction scheme of the transport layer is given. Then the key problems and solutions of JESD204B receiver interface are analyzed. In order to verify the performance of the designed JESD204B receiver interface, the simulation test and board-level measurement of the implemented JESD204B receiver interface are carried out. The simulation results show that: 1) the logic function of the JESD204B receiver interface is correct; 2) the timing analysis report given by Vivado meets the requirement of the circuit working frequency. The experimental results at the board level show that the function of the JESD204B receiver interface is correct and the operation is stable.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN79
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