高速展频时钟发生器的研究与设计

发布时间：2019-04-11 09:25

【摘要】：随着电子器件的工作速度越来越快,它们所引起的电磁干扰(EMI)的危害也越来越大。为了消除EMI,人们采取了很多方法,例如时钟信号采用低电压的差分时钟对,交错排列高频信号接口,版图设计时采纳特殊技术,以及应用展频时钟技术。在这些方法中,展频时钟技术能够消除更高次谐波的能量,从而能更有效地消弱EMI。除此之外展频时钟还能减少系统成本、缩短产品面市时间,更满足当前商业的需要。本文完成设计了一款800MHz频率,15dB的EMI衰减的展频锁相环。输出时钟满足了LPDDR3时序的要求。在matlab中搭建行为级模型,实现各个模块的线性模型,完成整个系统的功能验证。推导整个锁相环的传输函数,明确带宽、相位裕度等关键指标与电荷泵充放电流、振荡器增益、滤波器参数等部件之间的关系。对鉴频鉴相器的防死区脉冲的脉冲宽度进行优化,从电源抑制入手改善了压控振荡器的相位噪声表现,并深入分析了振荡器增益的取值会带来哪些影响,对其完善。针对展频锁相环环路带宽较窄,正常工作时达成锁定消耗时间较多的特点,自行设计改良了快速锁定模块。设计的高速同步分频器,对限制工作速度的关键逻辑节点重点设计,使分频器能够工作在1.04GHz左右的频率,为锁相环的正常工作留下30%的余量.本文采用的工艺是90 nm高压CMOS工艺,对锁相环完成了在各种环境下的仿真,展频和非展频工作状态都完成了验证,锁相环能够正常输出800MHz的,具有15dB的EMI衰减的时钟信号,展频情况下仿真得到cycle to cycle jitter的峰峰值为58ps,均方根值为25ps,达到了论文设立时的目标。
[Abstract]:As the electronic devices work faster and faster, the electromagnetic interference (EMI) caused by them is becoming more and more harmful. In order to eliminate EMI, many methods have been adopted, such as low voltage differential clock pairs for clock signals, interlaced high frequency signal interfaces, special techniques for layout design, and application of spread frequency clock technology. In these methods, the frequency spread clock technology can eliminate the higher harmonic energy and thus weaken the EMI. more effectively. In addition, frequency spread clock can reduce the system cost, shorten the time to market, and meet the needs of the current business. In this paper, a phase-locked loop with 800MHz frequency and EMI attenuation of 15dB is designed. The output clock meets the requirement of LPDDR3 timing. The behavior model is built in matlab, the linear model of each module is realized, and the function verification of the whole system is completed. The transfer function of the whole PLL is deduced, and the relations between the key parameters such as bandwidth, phase margin and charge pump charge-discharge current, oscillator gain and filter parameters are defined. The pulse width of the anti-dead-zone pulse of the frequency detector is optimized, the phase noise performance of the VCO is improved from the power supply suppression, and the influence of the gain value of the oscillator is analyzed in depth, and the perfection of the pulse width is also given. In view of the narrow bandwidth of frequency-spread phase-locked loop and the consuming time of achieving locking in normal operation, a fast locking module is designed and improved. The design of the high-speed synchronous frequency divider focuses on the key logic nodes which limit the working speed, which enables the divider to work at the frequency of about 1.04GHz, leaving 30% of the allowance for the normal operation of phase-locked loop (PLL). The technology used in this paper is 90 nm high-voltage CMOS process. The phase-locked loop is simulated in various environments, and the working states of spread frequency and non-spread frequency are verified. The PLL can normally output the clock signal of 800MHz with EMI attenuation of 15dB, and the phase-locked loop can normally output the clock signal with the attenuation of EMI of 15dB. Under the condition of spreading frequency, the peak and peak value of cycle to cycle jitter is 58 PS and RMS is 25 PS, which achieves the goal of the paper.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN602

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